cyclic.fit.qmsg

来自「基于fpga的屏幕测试程序」· QMSG 代码 · 共 53 行 · 第 1/5 页

{ "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED" "pin clk1_in " "Info: Promoted pin \"clk1_in\" with Global Signal logic option assignment" { { "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED_TO_LOCATION" "pin clk1_in PIN J4 " "Info: Assigned pin \"clk1_in\" to location PIN J4" {  } { { "D:/实验室/pg_070731/db/cyclic_cmp.qrpt" "" { Report "D:/实验室/pg_070731/db/cyclic_cmp.qrpt" Compiler "cyclic" "UNKNOWN" "V1" "D:/实验室/pg_070731/db/cyclic.quartus_db" { Floorplan "D:/实验室/pg_070731/" "" "" { clk1_in } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk1_in" } } } } { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 14 -1 0 } } { "D:/实验室/pg_070731/cyclic.fld" "" { Floorplan "D:/实验室/pg_070731/cyclic.fld" "" "" { clk1_in } "NODE_NAME" } }  } 0} { "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED_REGION" "Global clock the entire device " "Info: Fan-outs that use the Global signal logic option setting Global clock are assigned to the entire device" {  } {  } 0}  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk1_in" } } } } { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 14 -1 0 } } { "D:/实验室/pg_070731/db/cyclic_cmp.qrpt" "" { Report "D:/实验室/pg_070731/db/cyclic_cmp.qrpt" Compiler "cyclic" "UNKNOWN" "V1" "D:/实验室/pg_070731/db/cyclic.quartus_db" { Floorplan "D:/实验室/pg_070731/" "" "" { clk1_in } "NODE_NAME" } "" } } { "D:/实验室/pg_070731/cyclic.fld" "" { Floorplan "D:/实验室/pg_070731/cyclic.fld" "" "" { clk1_in } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED" "logic cell expander:i2c_expander\|klok_div_8\[2\] " "Info: Promoted logic cell \"expander:i2c_expander\|klok_div_8\[2\]\" with Global Signal logic option assignment" { { "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED_REGION" "Global clock the entire device " "Info: Fan-outs that use the Global signal logic option setting Global clock are assigned to the entire device" {  } {  } 0}  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "expander:i2c_expander\|klok_div_8\[2\]" } } } } { "expander.tdf" "" { Text "D:/实验室/pg_070731/expander.tdf" 29 11 0 } } { "D:/实验室/pg_070731/db/cyclic_cmp.qrpt" "" { Report "D:/实验室/pg_070731/db/cyclic_cmp.qrpt" Compiler "cyclic" "UNKNOWN" "V1" "D:/实验室/pg_070731/db/cyclic.quartus_db" { Floorplan "D:/实验室/pg_070731/" "" "" { expander:i2c_expander|klok_div_8[2] } "NODE_NAME" } "" } } { "D:/实验室/pg_070731/cyclic.fld" "" { Floorplan "D:/实验室/pg_070731/cyclic.fld" "" "" { expander:i2c_expander|klok_div_8[2] } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "dclk Global clock in PIN J3 " "Info: Automatically promoted some destinations of signal \"dclk\" to use Global clock in PIN J3" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clk_out1~8 " "Info: Destination \"clk_out1~8\" may be non-global or may not use global clock" {  } { { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 31 -1 0 } }  } 0}  } { { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 13 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fran_pg:pattern_generator\|start_v_delay~3 Global clock " "Info: Automatically promoted some destinations of signal \"fran_pg:pattern_generator\|start_v_delay~3\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fran_pg:pattern_generator\|serials:theserial\|trigger_dffe " "Info: Destination \"fran_pg:pattern_generator\|serials:theserial\|trigger_dffe\" may be non-global or may not use global clock" {  } { { "serials.tdf" "" { Text "D:/实验室/pg_070731/serials.tdf" 83 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fran_pg:pattern_generator\|serials_3L:theserial_3L\|trigger_dffe " "Info: Destination \"fran_pg:pattern_generator\|serials_3L:theserial_3L\|trigger_dffe\" may be non-global or may not use global clock" {  } { { "serials_3L.tdf" "" { Text "D:/实验室/pg_070731/serials_3L.tdf" 70 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fran_pg:pattern_generator\|serials:theserial\|s1 " "Info: Destination \"fran_pg:pattern_generator\|serials:theserial\|s1\" may be non-global or may not use global clock" {  } { { "serials.tdf" "" { Text "D:/实验室/pg_070731/serials.tdf" 70 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fran_pg:pattern_generator\|serials_3L:theserial_3L\|s1 " "Info: Destination \"fran_pg:pattern_generator\|serials_3L:theserial_3L\|s1\" may be non-global or may not use global clock" {  } { { "serials_3L.tdf" "" { Text "D:/实验室/pg_070731/serials_3L.tdf" 59 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fran_pg:pattern_generator\|serials:theserial\|s5 " "Info: Destination \"fran_pg:pattern_generator\|serials:theserial\|s5\" may be non-global or may not use global clock" {  } { { "serials.tdf" "" { Text "D:/实验室/pg_070731/serials.tdf" 70 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fran_pg:pattern_generator\|serials:theserial\|idle " "Info: Destination \"fran_pg:pattern_generator\|serials:theserial\|idle\" may be non-global or may not use global clock" {  } { { "serials.tdf" "" { Text "D:/实验室/pg_070731/serials.tdf" 70 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fran_pg:pattern_generator\|serials_3L:theserial_3L\|s3 " "Info: Destination \"fran_pg:pattern_generator\|serials_3L:theserial_3L\|s3\" may be non-global or may not use global clock" {  } { { "serials_3L.tdf" "" { Text "D:/实验室/pg_070731/serials_3L.tdf" 59 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fran_pg:pattern_generator\|serials_3L:theserial_3L\|idle " "Info: Destination \"fran_pg:pattern_generator\|serials_3L:theserial_3L\|idle\" may be non-global or may not use global clock" {  } { { "serials_3L.tdf" "" { Text "D:/实验室/pg_070731/serials_3L.tdf" 59 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fran_pg:pattern_generator\|serials:theserial\|s3 " "Info: Destination \"fran_pg:pattern_generator\|serials:theserial\|s3\" may be non-global or may not use global clock" {  } { { "serials.tdf" "" { Text "D:/实验室/pg_070731/serials.tdf" 70 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fran_pg:pattern_generator\|serials:theserial\|s2 " "Info: Destination \"fran_pg:pattern_generator\|serials:theserial\|s2\" may be non-global or may not use global clock" {  } { { "serials.tdf" "" { Text "D:/实验室/pg_070731/serials.tdf" 70 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "fran_pg.tdf" "" { Text "D:/实验室/pg_070731/fran_pg.tdf" 174 1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fran_pg:pattern_generator\|fullregbuf\[153\] Global clock " "Info: Automatically promoted signal \"fran_pg:pattern_generator\|fullregbuf\[153\]\" to use Global clock" {  } { { "fran_pg.tdf" "" { Text "D:/实验室/pg_070731/fran_pg.tdf" 160 11 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}