cyclic.fit.qmsg

来自「基于fpga的屏幕测试程序」· QMSG 代码 · 共 53 行 · 第 1/5 页

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVCMOS. " "Info: I/O standards used: LVCMOS." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 56 7 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 56 total pin(s) used --  7 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 52 1 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 52 total pin(s) used --  1 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 uses 1.25V 3.30V 25 39 " "Info: I/O bank number 3 uses 1.25V VREF pins and has 3.30V VCCIO pins. 25 total pin(s) used --  39 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 uses 1.25V 3.30V 21 32 " "Info: I/O bank number 4 uses 1.25V VREF pins and has 3.30V VCCIO pins. 21 total pin(s) used --  32 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_START" "" "Info: Starting physical synthesis optimizations" {  } {  } 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register retiming " "Info: Starting physical synthesis algorithm register retiming" {  } {  } 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "register retiming 0 " "Info: Physical synthesis algorithm register retiming complete: estimated performance improvement of up to 0 percent" {  } {  } 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis 1 " "Info: Starting physical synthesis algorithm combinational resynthesis 1" {  } {  } 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "combinational resynthesis 1 1 " "Info: Physical synthesis algorithm combinational resynthesis 1 complete: estimated performance improvement of up to 1 percent" {  } {  } 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "logic and register replication " "Info: Starting physical synthesis algorithm logic and register replication" {  } {  } 0}