cyclic.fit.qmsg

来自「基于fpga的屏幕测试程序」· QMSG 代码 · 共 53 行 · 第 1/5 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 29 16:47:03 2007 " "Info: Processing started: Sat Sep 29 16:47:03 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=on --write_settings_files=off cyclic -c cyclic " "Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off cyclic -c cyclic" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "cyclic EP1C20F324C6 " "Info: Selected device EP1C20F324C6 for design \"cyclic\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C4F324C6 " "Info: Device EP1C4F324C6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12F324C6 " "Info: Device EP1C12F324C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "1 153 " "Info: No exact pin location assignment(s) for 1 pins of 153 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "pd_out " "Info: Pin pd_out not assigned to an exact location on the device" {  } { { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 45 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pd_out" } } } } { "D:/实验室/pg_070731/db/cyclic_cmp.qrpt" "" { Report "D:/实验室/pg_070731/db/cyclic_cmp.qrpt" Compiler "cyclic" "UNKNOWN" "V1" "D:/实验室/pg_070731/db/cyclic.quartus_db" { Floorplan "D:/实验室/pg_070731/" "" "" { pd_out } "NODE_NAME" } "" } } { "D:/实验室/pg_070731/cyclic.fld" "" { Floorplan "D:/实验室/pg_070731/cyclic.fld" "" "" { pd_out } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}