prev_cmp_ctime.tan.qmsg

用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 10 09:29:25 2008 " "Info: Processing started: Thu Apr 10 09:29:25 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off ctime -c ctime --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ctime -c ctime --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "ten:U4\|a\[0\]\$latch " "Warning: Node \"ten:U4\|a\[0\]\$latch\" is a latch" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U1\|b\[0\]\$latch " "Warning: Node \"six:U1\|b\[0\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U1\|b\[2\]\$latch " "Warning: Node \"six:U1\|b\[2\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U1\|b\[3\]\$latch " "Warning: Node \"six:U1\|b\[3\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U1\|b\[1\]\$latch " "Warning: Node \"six:U1\|b\[1\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ten:U0\|cout " "Warning: Node \"ten:U0\|cout\" is a latch" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ten:U2\|a\[3\]\$latch " "Warning: Node \"ten:U2\|a\[3\]\$latch\" is a latch" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ten:U2\|a\[0\]\$latch " "Warning: Node \"ten:U2\|a\[0\]\$latch\" is a latch" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ten:U2\|a\[1\]\$latch " "Warning: Node \"ten:U2\|a\[1\]\$latch\" is a latch" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ten:U2\|a\[2\]\$latch " "Warning: Node \"ten:U2\|a\[2\]\$latch\" is a latch" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U1\|cou " "Warning: Node \"six:U1\|cou\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U3\|b\[0\]\$latch " "Warning: Node \"six:U3\|b\[0\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U3\|b\[1\]\$latch " "Warning: Node \"six:U3\|b\[1\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U3\|b\[2\]\$latch " "Warning: Node \"six:U3\|b\[2\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U3\|b\[3\]\$latch " "Warning: Node \"six:U3\|b\[3\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ten:U2\|cout " "Warning: Node \"ten:U2\|cout\" is a latch" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ten:U4\|a\[3\]\$latch " "Warning: Node \"ten:U4\|a\[3\]\$latch\" is a latch" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ten:U4\|a\[2\]\$latch " "Warning: Node \"ten:U4\|a\[2\]\$latch\" is a latch" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U3\|cou " "Warning: Node \"six:U3\|cou\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ten:U4\|a\[1\]\$latch " "Warning: Node \"ten:U4\|a\[1\]\$latch\" is a latch" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U5\|b\[0\]\$latch " "Warning: Node \"six:U5\|b\[0\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U5\|b\[2\]\$latch " "Warning: Node \"six:U5\|b\[2\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U5\|b\[3\]\$latch " "Warning: Node \"six:U5\|b\[3\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "six:U5\|b\[1\]\$latch " "Warning: Node \"six:U5\|b\[1\]\$latch\" is a latch" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ten:U4\|cout " "Warning: Node \"ten:U4\|cout\" is a latch" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "7 " "Warning: Found combinational loop of 7 nodes" { { "Warning" "WTAN_SCC_NODE" "ten:U0\|a~198 " "Warning: Node \"ten:U0\|a~198\"" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WTAN_SCC_NODE" "ten:U0\|Equal0~34 " "Warning: Node \"ten:U0\|Equal0~34\"" {  } { { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WTAN_SCC_NODE" "ten:U0\|a~197 " "Warning: Node \"ten:U0\|a~197\"" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WTAN_SCC_NODE" "ten:U0\|a~195 " "Warning: Node \"ten:U0\|a~195\"" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WTAN_SCC_NODE" "ten:U0\|Add0~104 " "Warning: Node \"ten:U0\|Add0~104\"" {  } { { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WTAN_SCC_NODE" "ten:U0\|a~196 " "Warning: Node \"ten:U0\|a~196\"" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WTAN_SCC_NODE" "ten:U0\|a~194 " "Warning: Node \"ten:U0\|a~194\"" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}