onebitadder.tan.qmsg

用VHDL语言采用串行方法实现用1位全加器实现4位全加器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 12 10:42:36 2008 " "Info: Processing started: Sat Apr 12 10:42:36 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off onebitadder -c onebitadder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off onebitadder -c onebitadder --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "cin sum 10.836 ns Longest " "Info: Longest tpd from source pin \"cin\" to destination pin \"sum\" is 10.836 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cin 1 PIN PIN_105 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_105; Fanout = 2; PIN Node = 'cin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "onebitadder.vhd" "" { Text "J:/EDA/f_adder/onebitadder.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.093 ns) + CELL(0.590 ns) 7.152 ns sum~15 2 COMB LC_X26_Y11_N4 1 " "Info: 2: + IC(5.093 ns) + CELL(0.590 ns) = 7.152 ns; Loc. = LC_X26_Y11_N4; Fanout = 1; COMB Node = 'sum~15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.683 ns" { cin sum~15 } "NODE_NAME" } } { "onebitadder.vhd" "" { Text "J:/EDA/f_adder/onebitadder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(2.124 ns) 10.836 ns sum 3 PIN PIN_96 0 " "Info: 3: + IC(1.560 ns) + CELL(2.124 ns) = 10.836 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'sum'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.684 ns" { sum~15 sum } "NODE_NAME" } } { "onebitadder.vhd" "" { Text "J:/EDA/f_adder/onebitadder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.183 ns ( 38.60 % ) " "Info: Total cell delay = 4.183 ns ( 38.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.653 ns ( 61.40 % ) " "Info: Total interconnect delay = 6.653 ns ( 61.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.836 ns" { cin sum~15 sum } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.836 ns" { cin cin~out0 sum~15 sum } { 0.000ns 0.000ns 5.093ns 1.560ns } { 0.000ns 1.469ns 0.590ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 12 10:42:37 2008 " "Info: Processing ended: Sat Apr 12 10:42:37 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}