controlunit.tan.summary

CPU设计中的controlunit源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.854 ns
From           : IR[4]
To             : CAR[3]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.440 ns
From           : control_signal[2]~reg0
To             : control_signal[2]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.880 ns
From           : flag[7]
To             : CAR[6]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 112.15 MHz ( period = 8.917 ns )
From           : lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg7
To             : CAR[5]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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