top.ide_des

来自「Core_PWM,verilog语言编写」· IDE_DES 代码 · 共 20 行

KEY IDE_DES_TOOL "Designer"
KEY IDE_DES_FAMILY "Fusion"
KEY IDE_DES_DIE "IR6X6M2"
KEY IDE_DES_PACKAGE "fg256"
KEY IDE_DES_TOP_CELL_NAME "top"
KEY IDE_DES_KEEP_PHY_CONSTR "TRUE"
KEY IDE_DES_KEEP_TIME_CONSTR "TRUE"
KEY IDE_DES_LAYOUT_DONE "TRUE"
KEY IDE_DES_BA_EXPORTED "TRUE"
KEY IDE_DES_ERROR_FOUND "FALSE"
KEY IDE_DES_ADB_PATH "D:\PWM\designer\impl1\top.adb"
LIST SOURCE_FILES
VALUE "D:\PWM\synthesis\top.edn;edn"
VALUE "D:\PWM\synthesis\top_sdc.sdc;sdc"
VALUE "D:\PWM\constraint\pwm_top.pdc;pdc"
ENDLIST
LIST OPTIONAL_FILES
VALUE "D:\PWM\synthesis\top_sdc.sdc;Used"
ENDLIST