control.plg

来自「Core_PWM,verilog语言编写」· PLG 代码 · 共 25 行

@P:  Worst Slack : 1.920
@P:  control|CLK48M - Estimated Frequency : 133.0 MHz
@P:  control|CLK48M - Requested Frequency : 100.0 MHz
@P:  control|CLK48M - Estimated Period : 7.521
@P:  control|CLK48M - Requested Period : 10.000
@P:  control|CLK48M - Slack : 2.479
@P:  control|count_inferred_clock[20] - Estimated Frequency : 166.6 MHz
@P:  control|count_inferred_clock[20] - Requested Frequency : 100.0 MHz
@P:  control|count_inferred_clock[20] - Estimated Period : 6.002
@P:  control|count_inferred_clock[20] - Requested Period : 10.000
@P:  control|count_inferred_clock[20] - Slack : 3.998
@P:  control|count_inferred_clock[21] - Estimated Frequency : 616.5 MHz
@P:  control|count_inferred_clock[21] - Requested Frequency : 100.0 MHz
@P:  control|count_inferred_clock[21] - Estimated Period : 1.622
@P:  control|count_inferred_clock[21] - Requested Period : 10.000
@P:  control|count_inferred_clock[21] - Slack : 8.378
@P:  control|count_inferred_clock[23] - Estimated Frequency : 123.8 MHz
@P:  control|count_inferred_clock[23] - Requested Frequency : 100.0 MHz
@P:  control|count_inferred_clock[23] - Estimated Period : 8.080
@P:  control|count_inferred_clock[23] - Requested Period : 10.000
@P:  control|count_inferred_clock[23] - Slack : 1.920
@P:  Total Area : 422.0
@P:  Total Area : 422.0
@P:  CPU Time : 0h:00m:05s