_primary.vhd

Core_PWM,verilog语言编写

library verilog;
use verilog.vl_types.all;
entity PLL_1 is
    port(
        PLL_1_VCC       : in     vl_logic;
        PLL_1_GND       : in     vl_logic;
        CLK48M_c        : in     vl_logic;
        GLA_i           : out    vl_logic
    );
end PLL_1;