_primary.vhd

来自「Core_PWM,verilog语言编写」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity control is
    port(
        data            : out    vl_logic_vector(7 downto 0);
        addr            : out    vl_logic_vector(2 downto 0);
        CLK48M_c        : in     vl_logic;
        rst_c           : in     vl_logic;
        WE              : out    vl_logic;
        CS              : out    vl_logic;
        N_108           : out    vl_logic;
        N_261           : out    vl_logic
    );
end control;