pll_1_work.ixf

来自「Core_PWM,verilog语言编写」· IXF 代码 · 共 1 行

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PLL_1</name><fileSets/><views/><vendorExtension><componentID name="PLL_1::work"/></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtension><coreDefFile path="./PLL_1/PLL_1.cxf"/></vendorExtension><model><signals><signal><name>POWERDOWN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>CLKA</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>LOCK</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>GLA</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>OADIVRST</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal></signals></model></Component>