sine_generator.fit.summary

在quartus 11 5.1 里用VHDL编写的正弦波发生器

Fitter Status : Successful - Thu Apr 17 10:04:08 2008
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : sine_generator
Top-level Entity Name : sine_generator
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 60 / 10,570 ( < 1 % )
Total pins : 19 / 336 ( 6 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )