sine_generator.map.rpt

在quartus 11 5.1 里用VHDL编写的正弦波发生器

; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 60    ;
;     -- Combinational with no register       ; 34    ;
;     -- Register only                        ; 12    ;
;     -- Combinational with a register        ; 14    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 31    ;
;     -- 3 input functions                    ; 13    ;
;     -- 2 input functions                    ; 4     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 50    ;
;     -- arithmetic mode                      ; 10    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 26    ;
;                                             ;       ;
; Total registers                             ; 26    ;
; Total logic cells in carry chains           ; 12    ;
; I/O pins                                    ; 19    ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 26    ;
; Total fan-out                               ; 269   ;
; Average fan-out                             ; 3.41  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------+
; |sine_generator            ; 60 (0)      ; 26           ; 0           ; 0            ; 0       ; 0         ; 0         ; 19   ; 0            ; 34 (0)       ; 12 (0)            ; 14 (0)           ; 12 (0)          ; 0 (0)      ; |sine_generator                    ;
;    |generator_acc6:U4|     ; 6 (6)       ; 6            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; 6 (6)           ; 0 (0)      ; |sine_generator|generator_acc6:U4  ;
;    |generator_adder:U3|    ; 6 (6)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; 6 (6)           ; 0 (0)      ; |sine_generator|generator_adder:U3 ;
;    |generator_and2:U8|     ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |sine_generator|generator_and2:U8  ;
;    |generator_and2:U9|     ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |sine_generator|generator_and2:U9  ;
;    |generator_reg6:U1|     ; 6 (6)       ; 6            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 6 (6)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |sine_generator|generator_reg6:U1  ;
;    |generator_reg6:U2|     ; 6 (6)       ; 6            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 6 (6)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |sine_generator|generator_reg6:U2  ;
;    |generator_reg8:U7|     ; 8 (8)       ; 8            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 0 (0)           ; 0 (0)      ; |sine_generator|generator_reg8:U7  ;
;    |generator_sin:U6|      ; 26 (26)     ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 26 (26)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |sine_generator|generator_sin:U6   ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 26    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 26    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 26    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 17 10:03:52 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sine_generator -c sine_generator
Warning: Using design file sine_generator.vhd, which is not specified as a design file for the current project, but contains definitions for 16 design units and 8 entities in project
    Info: Found design unit 1: generator_acc6-acc_arch
    Info: Found design unit 2: generator_mux-mux_arch
    Info: Found design unit 3: generator_adder-add_anGen_arch
    Info: Found design unit 4: generator_and2-and_anGen_arch
    Info: Found design unit 5: generator_sin-sin_arch
    Info: Found design unit 6: generator_reg6-reg_arch6
    Info: Found design unit 7: generator_reg8-reg_arch8
    Info: Found design unit 8: sine_generator-generator_arch
    Info: Found entity 1: generator_acc6
    Info: Found entity 2: generator_mux
    Info: Found entity 3: generator_adder
    Info: Found entity 4: generator_and2
    Info: Found entity 5: generator_sin
    Info: Found entity 6: generator_reg6
    Info: Found entity 7: generator_reg8
    Info: Found entity 8: sine_generator
Info: Elaborating entity "sine_generator" for the top level hierarchy
Info (10035): Verilog HDL or VHDL information at sine_generator.vhd(451): object "VAL1" declared but not used
Info (10035): Verilog HDL or VHDL information at sine_generator.vhd(452): object "VAL2" declared but not used
Info (10035): Verilog HDL or VHDL information at sine_generator.vhd(453): object "VAL3" declared but not used
Info: Elaborating entity "generator_reg6" for hierarchy "generator_reg6:U1"
Info: Elaborating entity "generator_sin" for hierarchy "generator_sin:U6"
Info (10425): VHDL Case Statement information at sine_generator.vhd(267): OTHERS choice is never selected
Info: Elaborating entity "generator_adder" for hierarchy "generator_adder:U3"
Info: Elaborating entity "generator_acc6" for hierarchy "generator_acc6:U4"
Info: Elaborating entity "generator_reg8" for hierarchy "generator_reg8:U7"
Info: Elaborating entity "generator_and2" for hierarchy "generator_and2:U8"
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "generator_sin:U6|Q[7]" that feeds logic to a wire
    Warning: Converting TRI node "generator_sin:U6|Q[6]" that feeds logic to a wire
    Warning: Converting TRI node "generator_sin:U6|Q[5]" that feeds logic to a wire
    Warning: Converting TRI node "generator_sin:U6|Q[4]" that feeds logic to a wire
    Warning: Converting TRI node "generator_sin:U6|Q[3]" that feeds logic to a wire
    Warning: Converting TRI node "generator_sin:U6|Q[2]" that feeds logic to a wire
    Warning: Converting TRI node "generator_sin:U6|Q[1]" that feeds logic to a wire
    Warning: Converting TRI node "generator_sin:U6|Q[0]" that feeds logic to a wire
Info: Implemented 79 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 8 output pins
    Info: Implemented 60 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Thu Apr 17 10:03:55 2008
    Info: Elapsed time: 00:00:04