sine_generator.fit.eqn

在quartus 11 5.1 里用VHDL编写的正弦波发生器

B1_TEMP_Q_0[4] = DFFEAS(B1_TEMP_Q_0[4]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G2_O, , , , );


--D1_REG_Q[1] is generator_acc6:U4|REG_Q[1] at LC_X44_Y11_N2
--operation mode is arithmetic

D1_REG_Q[1]_lut_out = D1_REG_Q[1] $ B2_TEMP_Q_0[1] $ D1L3;
D1_REG_Q[1] = DFFEAS(D1_REG_Q[1]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );

--D1L6 is generator_acc6:U4|REG_Q[1]~53 at LC_X44_Y11_N2
--operation mode is arithmetic

D1L6_cout_0 = D1_REG_Q[1] & !B2_TEMP_Q_0[1] & !D1L3 # !D1_REG_Q[1] & (!D1L3 # !B2_TEMP_Q_0[1]);
D1L6 = CARRY(D1L6_cout_0);

--D1L7 is generator_acc6:U4|REG_Q[1]~53COUT1_74 at LC_X44_Y11_N2
--operation mode is arithmetic

D1L7_cout_1 = D1_REG_Q[1] & !B2_TEMP_Q_0[1] & !D1L4 # !D1_REG_Q[1] & (!D1L4 # !B2_TEMP_Q_0[1]);
D1L7 = CARRY(D1L7_cout_1);


--B1_TEMP_Q_0[1] is generator_reg6:U1|TEMP_Q_0[1] at LC_X46_Y11_N5
--operation mode is normal

B1_TEMP_Q_0[1]_lut_out = DATA[1];
B1_TEMP_Q_0[1] = DFFEAS(B1_TEMP_Q_0[1]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G2_O, , , , );


--D1_REG_Q[5] is generator_acc6:U4|REG_Q[5] at LC_X44_Y11_N6
--operation mode is normal

D1_REG_Q[5]_carry_eqn = (!D1L12 & D1L16) # (D1L12 & D1L17);
D1_REG_Q[5]_lut_out = D1_REG_Q[5] $ D1_REG_Q[5]_carry_eqn $ B2_TEMP_Q_0[5];
D1_REG_Q[5] = DFFEAS(D1_REG_Q[5]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );


--B1_TEMP_Q_0[5] is generator_reg6:U1|TEMP_Q_0[5] at LC_X46_Y11_N8
--operation mode is normal

B1_TEMP_Q_0[5]_lut_out = DATA[5];
B1_TEMP_Q_0[5] = DFFEAS(B1_TEMP_Q_0[5]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G2_O, , , , );


--D1_REG_Q[2] is generator_acc6:U4|REG_Q[2] at LC_X44_Y11_N3
--operation mode is arithmetic

D1_REG_Q[2]_lut_out = B2_TEMP_Q_0[2] $ D1_REG_Q[2] $ !D1L6;
D1_REG_Q[2] = DFFEAS(D1_REG_Q[2]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );

--D1L9 is generator_acc6:U4|REG_Q[2]~61 at LC_X44_Y11_N3
--operation mode is arithmetic

D1L9_cout_0 = B2_TEMP_Q_0[2] & (D1_REG_Q[2] # !D1L6) # !B2_TEMP_Q_0[2] & D1_REG_Q[2] & !D1L6;
D1L9 = CARRY(D1L9_cout_0);

--D1L10 is generator_acc6:U4|REG_Q[2]~61COUT1 at LC_X44_Y11_N3
--operation mode is arithmetic

D1L10_cout_1 = B2_TEMP_Q_0[2] & (D1_REG_Q[2] # !D1L7) # !B2_TEMP_Q_0[2] & D1_REG_Q[2] & !D1L7;
D1L10 = CARRY(D1L10_cout_1);


--B1_TEMP_Q_0[2] is generator_reg6:U1|TEMP_Q_0[2] at LC_X46_Y11_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_TEMP_Q_0[2]_lut_out = GND;
B1_TEMP_Q_0[2] = DFFEAS(B1_TEMP_Q_0[2]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G2_O, DATA[2], , , VCC);


--D1_REG_Q[0] is generator_acc6:U4|REG_Q[0] at LC_X44_Y11_N1
--operation mode is arithmetic

D1_REG_Q[0]_lut_out = B2_TEMP_Q_0[0] $ D1_REG_Q[0];
D1_REG_Q[0] = DFFEAS(D1_REG_Q[0]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );

--D1L3 is generator_acc6:U4|REG_Q[0]~65 at LC_X44_Y11_N1
--operation mode is arithmetic

D1L3_cout_0 = B2_TEMP_Q_0[0] & D1_REG_Q[0];
D1L3 = CARRY(D1L3_cout_0);

--D1L4 is generator_acc6:U4|REG_Q[0]~65COUT1_73 at LC_X44_Y11_N1
--operation mode is arithmetic

D1L4_cout_1 = B2_TEMP_Q_0[0] & D1_REG_Q[0];
D1L4 = CARRY(D1L4_cout_1);


--B1_TEMP_Q_0[0] is generator_reg6:U1|TEMP_Q_0[0] at LC_X46_Y11_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_TEMP_Q_0[0]_lut_out = GND;
B1_TEMP_Q_0[0] = DFFEAS(B1_TEMP_Q_0[0]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G2_O, DATA[0], , , VCC);


--D1_REG_Q[3] is generator_acc6:U4|REG_Q[3] at LC_X44_Y11_N4
--operation mode is arithmetic

D1_REG_Q[3]_lut_out = D1_REG_Q[3] $ B2_TEMP_Q_0[3] $ D1L9;
D1_REG_Q[3] = DFFEAS(D1_REG_Q[3]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );

--D1L12 is generator_acc6:U4|REG_Q[3]~69 at LC_X44_Y11_N4
--operation mode is arithmetic

D1L12 = D1L13;


--B1_TEMP_Q_0[3] is generator_reg6:U1|TEMP_Q_0[3] at LC_X46_Y11_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_TEMP_Q_0[3]_lut_out = GND;
B1_TEMP_Q_0[3] = DFFEAS(B1_TEMP_Q_0[3]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G2_O, DATA[3], , , VCC);


--B2_TEMP_Q_0[4] is generator_reg6:U2|TEMP_Q_0[4] at LC_X46_Y11_N6
--operation mode is normal

B2_TEMP_Q_0[4]_lut_out = DATA[4];
B2_TEMP_Q_0[4] = DFFEAS(B2_TEMP_Q_0[4]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G1_O, , , , );


--G2_O is generator_and2:U9|O at LC_X46_Y11_N7
--operation mode is normal

G2_O = CE & (PR);


--B2_TEMP_Q_0[1] is generator_reg6:U2|TEMP_Q_0[1] at LC_X44_Y11_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B2_TEMP_Q_0[1]_lut_out = GND;
B2_TEMP_Q_0[1] = DFFEAS(B2_TEMP_Q_0[1]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G1_O, DATA[1], , , VCC);


--B2_TEMP_Q_0[5] is generator_reg6:U2|TEMP_Q_0[5] at LC_X46_Y11_N1
--operation mode is normal

B2_TEMP_Q_0[5]_lut_out = DATA[5];
B2_TEMP_Q_0[5] = DFFEAS(B2_TEMP_Q_0[5]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G1_O, , , , );


--B2_TEMP_Q_0[2] is generator_reg6:U2|TEMP_Q_0[2] at LC_X44_Y11_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B2_TEMP_Q_0[2]_lut_out = GND;
B2_TEMP_Q_0[2] = DFFEAS(B2_TEMP_Q_0[2]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G1_O, DATA[2], , , VCC);


--B2_TEMP_Q_0[0] is generator_reg6:U2|TEMP_Q_0[0] at LC_X44_Y11_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B2_TEMP_Q_0[0]_lut_out = GND;
B2_TEMP_Q_0[0] = DFFEAS(B2_TEMP_Q_0[0]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G1_O, DATA[0], , , VCC);


--B2_TEMP_Q_0[3] is generator_reg6:U2|TEMP_Q_0[3] at LC_X44_Y11_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B2_TEMP_Q_0[3]_lut_out = GND;
B2_TEMP_Q_0[3] = DFFEAS(B2_TEMP_Q_0[3]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , G1_O, DATA[3], , , VCC);


--G1_O is generator_and2:U8|O at LC_X46_Y11_N3
--operation mode is normal

G1_O = CE & (FR);


--E1L23 is generator_sin:U6|Mux~1335 at LC_X45_Y12_N0
--operation mode is normal

E1L23 = C1L8 & E1L21 & (!C1L1 # !C1L7) # !C1L8 & !E1L21 & (C1L7 # C1L1);


--E1L24 is generator_sin:U6|Mux~1337 at LC_X44_Y12_N3
--operation mode is normal

E1L24 = E1L20 $ (C1L8 & (E1L19 # !C1L7) # !C1L8 & E1L19 & !C1L7);


--E1L25 is generator_sin:U6|Mux~1339 at LC_X45_Y11_N8
--operation mode is normal

E1L25 = E1L13 $ (C1L8 & (!E1L12 # !C1L11) # !C1L8 & (E1L12));


--E1L26 is generator_sin:U6|Mux~1341 at LC_X46_Y12_N8
--operation mode is normal

E1L26 = C1L7 & (E1L6 $ !C1L1) # !C1L7 & (E1L5 $ (E1L6 & C1L1));


--CLK is CLK at PIN_L2
--operation mode is input

CLK = INPUT();


--CLR is CLR at PIN_L3
--operation mode is input

CLR = INPUT();


--CE is CE at PIN_W7
--operation mode is input

CE = INPUT();


--DATA[4] is DATA[4] at PIN_M1
--operation mode is input

DATA[4] = INPUT();


--PR is PR at PIN_M2
--operation mode is input

PR = INPUT();


--DATA[1] is DATA[1] at PIN_AB7
--operation mode is input

DATA[1] = INPUT();


--DATA[5] is DATA[5] at PIN_AA6
--operation mode is input

DATA[5] = INPUT();


--DATA[2] is DATA[2] at PIN_N3
--operation mode is input

DATA[2] = INPUT();


--DATA[0] is DATA[0] at PIN_N2
--operation mode is input

DATA[0] = INPUT();


--DATA[3] is DATA[3] at PIN_Y6
--operation mode is input

DATA[3] = INPUT();


--FR is FR at PIN_V7
--operation mode is input

FR = INPUT();


--Q[0] is Q[0] at PIN_Y7
--operation mode is output

Q[0] = OUTPUT(F1_TEMP_Q_1[0]);


--Q[1] is Q[1] at PIN_B7
--operation mode is output

Q[1] = OUTPUT(F1_TEMP_Q_1[1]);


--Q[2] is Q[2] at PIN_D7
--operation mode is output

Q[2] = OUTPUT(F1_TEMP_Q_1[2]);


--Q[3] is Q[3] at PIN_E7
--operation mode is output

Q[3] = OUTPUT(F1_TEMP_Q_1[3]);


--Q[4] is Q[4] at PIN_U6
--operation mode is output

Q[4] = OUTPUT(F1_TEMP_Q_1[4]);


--Q[5] is Q[5] at PIN_AA7
--operation mode is output

Q[5] = OUTPUT(F1_TEMP_Q_1[5]);


--Q[6] is Q[6] at PIN_V5
--operation mode is output

Q[6] = OUTPUT(F1_TEMP_Q_1[6]);


--Q[7] is Q[7] at PIN_P2
--operation mode is output

Q[7] = OUTPUT(F1_TEMP_Q_1[7]);