sine_generator.fit.eqn

在quartus 11 5.1 里用VHDL编写的正弦波发生器

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--F1_TEMP_Q_1[0] is generator_reg8:U7|TEMP_Q_1[0] at LC_X46_Y12_N2
--operation mode is normal

F1_TEMP_Q_1[0]_lut_out = E1L3 $ (E1L4 # C1L1);
F1_TEMP_Q_1[0] = DFFEAS(F1_TEMP_Q_1[0]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );


--F1_TEMP_Q_1[1] is generator_reg8:U7|TEMP_Q_1[1] at LC_X46_Y12_N5
--operation mode is normal

F1_TEMP_Q_1[1]_lut_out = E1L26 & (C1L1 & (C1L14 # C1L7) # !C1L1 & (!C1L7 # !C1L14));
F1_TEMP_Q_1[1] = DFFEAS(F1_TEMP_Q_1[1]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );


--F1_TEMP_Q_1[2] is generator_reg8:U7|TEMP_Q_1[2] at LC_X44_Y12_N4
--operation mode is normal

F1_TEMP_Q_1[2]_lut_out = E1L10 & (!C1L11 # !E1L11) # !E1L10 & (E1L7 & C1L11);
F1_TEMP_Q_1[2] = DFFEAS(F1_TEMP_Q_1[2]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );


--F1_TEMP_Q_1[3] is generator_reg8:U7|TEMP_Q_1[3] at LC_X45_Y11_N9
--operation mode is normal

F1_TEMP_Q_1[3]_lut_out = E1L12 & (C1L4 # E1L25) # !E1L12 & E1L25 & (C1L4 $ C1L11);
F1_TEMP_Q_1[3] = DFFEAS(F1_TEMP_Q_1[3]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );


--F1_TEMP_Q_1[4] is generator_reg8:U7|TEMP_Q_1[4] at LC_X45_Y12_N4
--operation mode is normal

F1_TEMP_Q_1[4]_lut_out = E1L17 & (E1L18 # !C1L8) # !E1L17 & E1L14 & C1L8;
F1_TEMP_Q_1[4] = DFFEAS(F1_TEMP_Q_1[4]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );


--F1_TEMP_Q_1[5] is generator_reg8:U7|TEMP_Q_1[5] at LC_X44_Y12_N6
--operation mode is normal

F1_TEMP_Q_1[5]_lut_out = C1L14 & (E1L19 & (!C1L7) # !E1L19 & E1L24) # !C1L14 & (E1L19 & E1L24 # !E1L19 & (C1L7));
F1_TEMP_Q_1[5] = DFFEAS(F1_TEMP_Q_1[5]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );


--F1_TEMP_Q_1[6] is generator_reg8:U7|TEMP_Q_1[6] at LC_X46_Y12_N3
--operation mode is normal

F1_TEMP_Q_1[6]_lut_out = C1L1 & (C1L14 & !C1L7 # !C1L14 & (E1L23)) # !C1L1 & (C1L14 & (E1L23) # !C1L14 & C1L7);
F1_TEMP_Q_1[6] = DFFEAS(F1_TEMP_Q_1[6]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );


--F1_TEMP_Q_1[7] is generator_reg8:U7|TEMP_Q_1[7] at LC_X44_Y12_N5
--operation mode is normal

F1_TEMP_Q_1[7]_lut_out = C1L1 & !C1L7 & (C1L14 # E1L22) # !C1L1 & C1L7 & (!E1L22 # !C1L14);
F1_TEMP_Q_1[7] = DFFEAS(F1_TEMP_Q_1[7]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );


--C1L1 is generator_adder:U3|add~110 at LC_X45_Y11_N5
--operation mode is arithmetic

C1L1_carry_eqn = (!C1L15 & GND) # (C1L15 & VCC);
C1L1 = D1_REG_Q[4] $ B1_TEMP_Q_0[4] $ !C1L1_carry_eqn;

--C1L2 is generator_adder:U3|add~112 at LC_X45_Y11_N5
--operation mode is arithmetic

C1L2_cout_0 = D1_REG_Q[4] & (B1_TEMP_Q_0[4] # !C1L15) # !D1_REG_Q[4] & B1_TEMP_Q_0[4] & !C1L15;
C1L2 = CARRY(C1L2_cout_0);

--C1L3 is generator_adder:U3|add~112COUT1_143 at LC_X45_Y11_N5
--operation mode is arithmetic

C1L3_cout_1 = D1_REG_Q[4] & (B1_TEMP_Q_0[4] # !C1L15) # !D1_REG_Q[4] & B1_TEMP_Q_0[4] & !C1L15;
C1L3 = CARRY(C1L3_cout_1);


--C1L4 is generator_adder:U3|add~115 at LC_X45_Y11_N2
--operation mode is arithmetic

C1L4 = B1_TEMP_Q_0[1] $ D1_REG_Q[1] $ C1L12;

--C1L5 is generator_adder:U3|add~117 at LC_X45_Y11_N2
--operation mode is arithmetic

C1L5_cout_0 = B1_TEMP_Q_0[1] & !D1_REG_Q[1] & !C1L12 # !B1_TEMP_Q_0[1] & (!C1L12 # !D1_REG_Q[1]);
C1L5 = CARRY(C1L5_cout_0);

--C1L6 is generator_adder:U3|add~117COUT1_142 at LC_X45_Y11_N2
--operation mode is arithmetic

C1L6_cout_1 = B1_TEMP_Q_0[1] & !D1_REG_Q[1] & !C1L13 # !B1_TEMP_Q_0[1] & (!C1L13 # !D1_REG_Q[1]);
C1L6 = CARRY(C1L6_cout_1);


--C1L7 is generator_adder:U3|add~120 at LC_X45_Y11_N6
--operation mode is normal

C1L7_carry_eqn = (!C1L15 & C1L2) # (C1L15 & C1L3);
C1L7 = B1_TEMP_Q_0[5] $ C1L7_carry_eqn $ D1_REG_Q[5];


--C1L8 is generator_adder:U3|add~125 at LC_X45_Y11_N3
--operation mode is arithmetic

C1L8 = B1_TEMP_Q_0[2] $ D1_REG_Q[2] $ !C1L5;

--C1L9 is generator_adder:U3|add~127 at LC_X45_Y11_N3
--operation mode is arithmetic

C1L9_cout_0 = B1_TEMP_Q_0[2] & (D1_REG_Q[2] # !C1L5) # !B1_TEMP_Q_0[2] & D1_REG_Q[2] & !C1L5;
C1L9 = CARRY(C1L9_cout_0);

--C1L10 is generator_adder:U3|add~127COUT1 at LC_X45_Y11_N3
--operation mode is arithmetic

C1L10_cout_1 = B1_TEMP_Q_0[2] & (D1_REG_Q[2] # !C1L6) # !B1_TEMP_Q_0[2] & D1_REG_Q[2] & !C1L6;
C1L10 = CARRY(C1L10_cout_1);


--C1L11 is generator_adder:U3|add~130 at LC_X45_Y11_N1
--operation mode is arithmetic

C1L11 = D1_REG_Q[0] $ B1_TEMP_Q_0[0];

--C1L12 is generator_adder:U3|add~132 at LC_X45_Y11_N1
--operation mode is arithmetic

C1L12_cout_0 = D1_REG_Q[0] & B1_TEMP_Q_0[0];
C1L12 = CARRY(C1L12_cout_0);

--C1L13 is generator_adder:U3|add~132COUT1_141 at LC_X45_Y11_N1
--operation mode is arithmetic

C1L13_cout_1 = D1_REG_Q[0] & B1_TEMP_Q_0[0];
C1L13 = CARRY(C1L13_cout_1);


--C1L14 is generator_adder:U3|add~135 at LC_X45_Y11_N4
--operation mode is arithmetic

C1L14 = D1_REG_Q[3] $ B1_TEMP_Q_0[3] $ C1L9;

--C1L15 is generator_adder:U3|add~137 at LC_X45_Y11_N4
--operation mode is arithmetic

C1L15 = C1L16;


--E1L1 is generator_sin:U6|Mux~1309 at LC_X46_Y12_N7
--operation mode is normal

E1L1 = C1L14 # C1L8 $ (!C1L7 & C1L11);


--E1L2 is generator_sin:U6|Mux~1310 at LC_X46_Y12_N0
--operation mode is normal

E1L2 = C1L7 & C1L11 & (C1L14 # !C1L8) # !C1L7 & C1L8 & (C1L14 # C1L11);


--E1L3 is generator_sin:U6|Mux~1311 at LC_X46_Y12_N1
--operation mode is normal

E1L3 = E1L1 & (C1L7 $ (!C1L4 # !E1L2)) # !E1L1 & (E1L2 & (!C1L7 # !C1L4) # !E1L2 & C1L4);


--E1L4 is generator_sin:U6|Mux~1312 at LC_X46_Y12_N6
--operation mode is normal

E1L4 = E1L1 & E1L2 & C1L4 & C1L7 # !E1L1 & !C1L4 & (E1L2 $ C1L7);


--E1L5 is generator_sin:U6|Mux~1314 at LC_X46_Y12_N4
--operation mode is normal

E1L5 = C1L8 & (C1L4 $ (!C1L11 # !C1L1)) # !C1L8 & (C1L4 & !C1L11);


--E1L6 is generator_sin:U6|Mux~1315 at LC_X46_Y12_N9
--operation mode is normal

E1L6 = C1L8 & (C1L11 $ (C1L1 # !C1L4)) # !C1L8 & C1L4 & (C1L11);


--E1L7 is generator_sin:U6|Mux~1316 at LC_X44_Y12_N0
--operation mode is normal

E1L7 = C1L8 & (C1L7) # !C1L8 & (C1L7 & (C1L14 # !C1L4) # !C1L7 & (C1L4));


--E1L8 is generator_sin:U6|Mux~1317 at LC_X45_Y12_N9
--operation mode is normal

E1L8 = C1L7 & C1L8 & (C1L14 $ !C1L4) # !C1L7 & C1L14 & !C1L8 & C1L4;


--E1L9 is generator_sin:U6|Mux~1318 at LC_X44_Y12_N1
--operation mode is normal

E1L9 = C1L4 & (C1L14 # C1L8 $ C1L7) # !C1L4 & (C1L7 # C1L8 $ C1L14);


--E1L10 is generator_sin:U6|Mux~1319 at LC_X44_Y12_N7
--operation mode is normal

E1L10 = C1L1 & (C1L11 # !E1L8) # !C1L1 & (E1L9 & !C1L11);


--E1L11 is generator_sin:U6|Mux~1320 at LC_X45_Y12_N1
--operation mode is normal

E1L11 = C1L7 & (C1L4 # !C1L8) # !C1L7 & C1L14 & C1L8 & !C1L4;


--E1L12 is generator_sin:U6|Mux~1322 at LC_X45_Y11_N0
--operation mode is normal

E1L12 = C1L14 & (C1L8 & !C1L7 # !C1L8 & (C1L1)) # !C1L14 & C1L7 & (C1L8 $ !C1L1);


--E1L13 is generator_sin:U6|Mux~1323 at LC_X45_Y11_N7
--operation mode is normal

E1L13 = C1L14 & (C1L1 # C1L7 $ !C1L8) # !C1L14 & C1L1 & (C1L7 $ C1L8);


--E1L14 is generator_sin:U6|Mux~1324 at LC_X45_Y12_N6
--operation mode is normal

E1L14 = C1L7 & (C1L1 $ (C1L14 # !C1L4)) # !C1L7 & (C1L1 # C1L14 & C1L4);


--E1L15 is generator_sin:U6|Mux~1325 at LC_X45_Y12_N5
--operation mode is normal

E1L15 = C1L7 & (C1L14 $ (C1L4 # !C1L1)) # !C1L7 & C1L14 & !C1L1 & !C1L4;


--E1L16 is generator_sin:U6|Mux~1326 at LC_X45_Y12_N7
--operation mode is normal

E1L16 = C1L14 & (!C1L4 # !C1L1) # !C1L14 & (C1L7 # C1L1);


--E1L17 is generator_sin:U6|Mux~1327 at LC_X45_Y12_N2
--operation mode is normal

E1L17 = C1L8 & (C1L11) # !C1L8 & (C1L11 & (E1L15) # !C1L11 & E1L16);


--E1L18 is generator_sin:U6|Mux~1328 at LC_X45_Y12_N3
--operation mode is normal

E1L18 = C1L7 & !C1L14 & C1L1 & C1L4 # !C1L7 & (C1L14 $ (!C1L1 & C1L4));


--E1L19 is generator_sin:U6|Mux~1330 at LC_X44_Y12_N9
--operation mode is normal

E1L19 = C1L1 & (C1L4 # C1L7 # C1L11);


--E1L20 is generator_sin:U6|Mux~1331 at LC_X44_Y12_N2
--operation mode is normal

E1L20 = C1L4 & (C1L7 # C1L11);


--E1L21 is generator_sin:U6|Mux~1332 at LC_X45_Y12_N8
--operation mode is normal

E1L21 = C1L4 & (C1L7 # C1L11);


--E1L22 is generator_sin:U6|Mux~1333 at LC_X44_Y12_N8
--operation mode is normal

E1L22 = C1L8 & (C1L4 # C1L1) # !C1L8 & C1L4 & C1L1 & C1L11;


--D1_REG_Q[4] is generator_acc6:U4|REG_Q[4] at LC_X44_Y11_N5
--operation mode is arithmetic

D1_REG_Q[4]_carry_eqn = (!D1L12 & GND) # (D1L12 & VCC);
D1_REG_Q[4]_lut_out = B2_TEMP_Q_0[4] $ D1_REG_Q[4] $ !D1_REG_Q[4]_carry_eqn;
D1_REG_Q[4] = DFFEAS(D1_REG_Q[4]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , CE, , , , );

--D1L16 is generator_acc6:U4|REG_Q[4]~49 at LC_X44_Y11_N5
--operation mode is arithmetic

D1L16_cout_0 = B2_TEMP_Q_0[4] & (D1_REG_Q[4] # !D1L12) # !B2_TEMP_Q_0[4] & D1_REG_Q[4] & !D1L12;
D1L16 = CARRY(D1L16_cout_0);

--D1L17 is generator_acc6:U4|REG_Q[4]~49COUT1_75 at LC_X44_Y11_N5
--operation mode is arithmetic

D1L17_cout_1 = B2_TEMP_Q_0[4] & (D1_REG_Q[4] # !D1L12) # !B2_TEMP_Q_0[4] & D1_REG_Q[4] & !D1L12;
D1L17 = CARRY(D1L17_cout_1);


--B1_TEMP_Q_0[4] is generator_reg6:U1|TEMP_Q_0[4] at LC_X46_Y11_N9
--operation mode is normal

B1_TEMP_Q_0[4]_lut_out = DATA[4];