sine_generator.map.summary

来自「在quartus 11 5.1 里用VHDL编写的正弦波发生器」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Thu Apr 17 10:03:55 2008
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : sine_generator
Top-level Entity Name : sine_generator
Family : Stratix
Total logic elements : 60
Total pins : 19
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0