sine_generator.tan.rpt

在quartus 11 5.1 里用VHDL编写的正弦波发生器

Timing Analyzer report for sine_generator
Thu Apr 17 10:04:15 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                        ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------+-------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                          ; To                            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------+-------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.423 ns                         ; CE                            ; generator_reg6:U2|TEMP_Q_0[0] ; --         ; CLK      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.531 ns                         ; generator_reg8:U7|TEMP_Q_1[6] ; Q[6]                          ; CLK        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -1.886 ns                        ; DATA[2]                       ; generator_reg6:U1|TEMP_Q_0[2] ; --         ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 203.09 MHz ( period = 4.924 ns ) ; generator_acc6:U4|REG_Q[3]    ; generator_reg8:U7|TEMP_Q_1[4] ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                               ;                               ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------+-------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                 ;
+-------+------------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                          ; To                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 203.09 MHz ( period = 4.924 ns )               ; generator_acc6:U4|REG_Q[3]    ; generator_reg8:U7|TEMP_Q_1[4] ; CLK        ; CLK      ; None                        ; None                      ; 4.768 ns                ;
; N/A   ; 204.92 MHz ( period = 4.880 ns )               ; generator_acc6:U4|REG_Q[3]    ; generator_reg8:U7|TEMP_Q_1[1] ; CLK        ; CLK      ; None                        ; None                      ; 4.724 ns                ;
; N/A   ; 206.57 MHz ( period = 4.841 ns )               ; generator_acc6:U4|REG_Q[0]    ; generator_reg8:U7|TEMP_Q_1[4] ; CLK        ; CLK      ; None                        ; None                      ; 4.685 ns                ;
; N/A   ; 207.04 MHz ( period = 4.830 ns )               ; generator_acc6:U4|REG_Q[3]    ; generator_reg8:U7|TEMP_Q_1[5] ; CLK        ; CLK      ; None                        ; None                      ; 4.674 ns                ;
; N/A   ; 208.16 MHz ( period = 4.804 ns )               ; generator_acc6:U4|REG_Q[3]    ; generator_reg8:U7|TEMP_Q_1[2] ; CLK        ; CLK      ; None                        ; None                      ; 4.648 ns                ;
; N/A   ; 208.46 MHz ( period = 4.797 ns )               ; generator_acc6:U4|REG_Q[0]    ; generator_reg8:U7|TEMP_Q_1[1] ; CLK        ; CLK      ; None                        ; None                      ; 4.641 ns                ;
; N/A   ; 209.38 MHz ( period = 4.776 ns )               ; generator_reg6:U1|TEMP_Q_0[1] ; generator_reg8:U7|TEMP_Q_1[4] ; CLK        ; CLK      ; None                        ; None                      ; 4.620 ns                ;
; N/A   ; 210.08 MHz ( period = 4.760 ns )               ; generator_acc6:U4|REG_Q[3]    ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; None                        ; None                      ; 4.604 ns                ;
; N/A   ; 210.66 MHz ( period = 4.747 ns )               ; generator_acc6:U4|REG_Q[0]    ; generator_reg8:U7|TEMP_Q_1[5] ; CLK        ; CLK      ; None                        ; None                      ; 4.591 ns                ;
; N/A   ; 211.33 MHz ( period = 4.732 ns )               ; generator_reg6:U1|TEMP_Q_0[1] ; generator_reg8:U7|TEMP_Q_1[1] ; CLK        ; CLK      ; None                        ; None                      ; 4.576 ns                ;
; N/A   ; 211.64 MHz ( period = 4.725 ns )               ; generator_reg6:U1|TEMP_Q_0[0] ; generator_reg8:U7|TEMP_Q_1[4] ; CLK        ; CLK      ; None                        ; None                      ; 4.569 ns                ;
; N/A   ; 211.82 MHz ( period = 4.721 ns )               ; generator_acc6:U4|REG_Q[0]    ; generator_reg8:U7|TEMP_Q_1[2] ; CLK        ; CLK      ; None                        ; None                      ; 4.565 ns                ;
; N/A   ; 211.91 MHz ( period = 4.719 ns )               ; generator_reg6:U1|TEMP_Q_0[2] ; generator_reg8:U7|TEMP_Q_1[4] ; CLK        ; CLK      ; None                        ; None                      ; 4.563 ns                ;
; N/A   ; 213.58 MHz ( period = 4.682 ns )               ; generator_reg6:U1|TEMP_Q_0[1] ; generator_reg8:U7|TEMP_Q_1[5] ; CLK        ; CLK      ; None                        ; None                      ; 4.526 ns                ;
; N/A   ; 213.63 MHz ( period = 4.681 ns )               ; generator_reg6:U1|TEMP_Q_0[0] ; generator_reg8:U7|TEMP_Q_1[1] ; CLK        ; CLK      ; None                        ; None                      ; 4.525 ns                ;
; N/A   ; 213.77 MHz ( period = 4.678 ns )               ; generator_acc6:U4|REG_Q[1]    ; generator_reg8:U7|TEMP_Q_1[4] ; CLK        ; CLK      ; None                        ; None                      ; 4.522 ns                ;
; N/A   ; 213.81 MHz ( period = 4.677 ns )               ; generator_acc6:U4|REG_Q[0]    ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; None                        ; None                      ; 4.521 ns                ;
; N/A   ; 213.90 MHz ( period = 4.675 ns )               ; generator_reg6:U1|TEMP_Q_0[2] ; generator_reg8:U7|TEMP_Q_1[1] ; CLK        ; CLK      ; None                        ; None                      ; 4.519 ns                ;
; N/A   ; 214.78 MHz ( period = 4.656 ns )               ; generator_reg6:U1|TEMP_Q_0[1] ; generator_reg8:U7|TEMP_Q_1[2] ; CLK        ; CLK      ; None                        ; None                      ; 4.500 ns                ;