sine_generator.map.eqn

在quartus 11 5.1 里用VHDL编写的正弦波发生器

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--F1_TEMP_Q_1[0] is generator_reg8:U7|TEMP_Q_1[0]
--operation mode is normal

F1_TEMP_Q_1[0]_lut_out = E1L3 $ (C1L1 # E1L4);
F1_TEMP_Q_1[0] = DFFEAS(F1_TEMP_Q_1[0]_lut_out, CLK, !CLR, , CE, , , , );


--F1_TEMP_Q_1[1] is generator_reg8:U7|TEMP_Q_1[1]
--operation mode is normal

F1_TEMP_Q_1[1]_lut_out = E1L26 & (C1L1 & (C1L5 # C1L10) # !C1L1 & (!C1L10 # !C1L5));
F1_TEMP_Q_1[1] = DFFEAS(F1_TEMP_Q_1[1]_lut_out, CLK, !CLR, , CE, , , , );


--F1_TEMP_Q_1[2] is generator_reg8:U7|TEMP_Q_1[2]
--operation mode is normal

F1_TEMP_Q_1[2]_lut_out = C1L8 & (E1L10 & (!E1L11) # !E1L10 & E1L7) # !C1L8 & (E1L10);
F1_TEMP_Q_1[2] = DFFEAS(F1_TEMP_Q_1[2]_lut_out, CLK, !CLR, , CE, , , , );


--F1_TEMP_Q_1[3] is generator_reg8:U7|TEMP_Q_1[3]
--operation mode is normal

F1_TEMP_Q_1[3]_lut_out = E1L12 & (E1L25 # C1L3) # !E1L12 & E1L25 & (C1L8 $ C1L3);
F1_TEMP_Q_1[3] = DFFEAS(F1_TEMP_Q_1[3]_lut_out, CLK, !CLR, , CE, , , , );


--F1_TEMP_Q_1[4] is generator_reg8:U7|TEMP_Q_1[4]
--operation mode is normal

F1_TEMP_Q_1[4]_lut_out = C1L6 & (E1L17 & (E1L18) # !E1L17 & E1L14) # !C1L6 & (E1L17);
F1_TEMP_Q_1[4] = DFFEAS(F1_TEMP_Q_1[4]_lut_out, CLK, !CLR, , CE, , , , );


--F1_TEMP_Q_1[5] is generator_reg8:U7|TEMP_Q_1[5]
--operation mode is normal

F1_TEMP_Q_1[5]_lut_out = E1L19 & (C1L10 & (!C1L5) # !C1L10 & E1L24) # !E1L19 & (C1L10 & E1L24 # !C1L10 & (C1L5));
F1_TEMP_Q_1[5] = DFFEAS(F1_TEMP_Q_1[5]_lut_out, CLK, !CLR, , CE, , , , );


--F1_TEMP_Q_1[6] is generator_reg8:U7|TEMP_Q_1[6]
--operation mode is normal

F1_TEMP_Q_1[6]_lut_out = C1L1 & (C1L10 & (!C1L5) # !C1L10 & E1L23) # !C1L1 & (C1L10 & E1L23 # !C1L10 & (C1L5));
F1_TEMP_Q_1[6] = DFFEAS(F1_TEMP_Q_1[6]_lut_out, CLK, !CLR, , CE, , , , );


--F1_TEMP_Q_1[7] is generator_reg8:U7|TEMP_Q_1[7]
--operation mode is normal

F1_TEMP_Q_1[7]_lut_out = C1L5 & !C1L1 & (!E1L22 # !C1L10) # !C1L5 & C1L1 & (C1L10 # E1L22);
F1_TEMP_Q_1[7] = DFFEAS(F1_TEMP_Q_1[7]_lut_out, CLK, !CLR, , CE, , , , );


--C1L1 is generator_adder:U3|add~110
--operation mode is arithmetic

C1L1_carry_eqn = C1L11;
C1L1 = D1_REG_Q[4] $ B1_TEMP_Q_0[4] $ !C1L1_carry_eqn;

--C1L2 is generator_adder:U3|add~112
--operation mode is arithmetic

C1L2 = CARRY(D1_REG_Q[4] & (B1_TEMP_Q_0[4] # !C1L11) # !D1_REG_Q[4] & B1_TEMP_Q_0[4] & !C1L11);


--C1L3 is generator_adder:U3|add~115
--operation mode is arithmetic

C1L3_carry_eqn = C1L9;
C1L3 = D1_REG_Q[1] $ B1_TEMP_Q_0[1] $ C1L3_carry_eqn;

--C1L4 is generator_adder:U3|add~117
--operation mode is arithmetic

C1L4 = CARRY(D1_REG_Q[1] & !B1_TEMP_Q_0[1] & !C1L9 # !D1_REG_Q[1] & (!C1L9 # !B1_TEMP_Q_0[1]));


--C1L5 is generator_adder:U3|add~120
--operation mode is normal

C1L5_carry_eqn = C1L2;
C1L5 = D1_REG_Q[5] $ B1_TEMP_Q_0[5] $ C1L5_carry_eqn;


--C1L6 is generator_adder:U3|add~125
--operation mode is arithmetic

C1L6_carry_eqn = C1L4;
C1L6 = D1_REG_Q[2] $ B1_TEMP_Q_0[2] $ !C1L6_carry_eqn;

--C1L7 is generator_adder:U3|add~127
--operation mode is arithmetic

C1L7 = CARRY(D1_REG_Q[2] & (B1_TEMP_Q_0[2] # !C1L4) # !D1_REG_Q[2] & B1_TEMP_Q_0[2] & !C1L4);


--C1L8 is generator_adder:U3|add~130
--operation mode is arithmetic

C1L8 = D1_REG_Q[0] $ B1_TEMP_Q_0[0];

--C1L9 is generator_adder:U3|add~132
--operation mode is arithmetic

C1L9 = CARRY(D1_REG_Q[0] & B1_TEMP_Q_0[0]);


--C1L10 is generator_adder:U3|add~135
--operation mode is arithmetic

C1L10_carry_eqn = C1L7;
C1L10 = D1_REG_Q[3] $ B1_TEMP_Q_0[3] $ C1L10_carry_eqn;

--C1L11 is generator_adder:U3|add~137
--operation mode is arithmetic

C1L11 = CARRY(D1_REG_Q[3] & !B1_TEMP_Q_0[3] & !C1L7 # !D1_REG_Q[3] & (!C1L7 # !B1_TEMP_Q_0[3]));


--E1L1 is generator_sin:U6|Mux~1309
--operation mode is normal

E1L1 = C1L10 # C1L6 $ (!C1L5 & C1L8);


--E1L2 is generator_sin:U6|Mux~1310
--operation mode is normal

E1L2 = C1L5 & C1L8 & (C1L10 # !C1L6) # !C1L5 & C1L6 & (C1L8 # C1L10);


--E1L3 is generator_sin:U6|Mux~1311
--operation mode is normal

E1L3 = E1L1 & (C1L5 $ (!E1L2 # !C1L3)) # !E1L1 & (C1L3 & (!E1L2 # !C1L5) # !C1L3 & (E1L2));


--E1L4 is generator_sin:U6|Mux~1312
--operation mode is normal

E1L4 = C1L3 & C1L5 & E1L1 & E1L2 # !C1L3 & !E1L1 & (C1L5 $ E1L2);


--E1L5 is generator_sin:U6|Mux~1314
--operation mode is normal

E1L5 = C1L8 & C1L6 & (C1L3 $ !C1L1) # !C1L8 & (C1L3 $ (C1L6));


--E1L6 is generator_sin:U6|Mux~1315
--operation mode is normal

E1L6 = C1L3 & (C1L8 $ (C1L1 & C1L6)) # !C1L3 & (!C1L8 & C1L6);


--E1L7 is generator_sin:U6|Mux~1316
--operation mode is normal

E1L7 = C1L5 & (C1L6 # C1L10 # !C1L3) # !C1L5 & C1L3 & !C1L6;


--E1L8 is generator_sin:U6|Mux~1317
--operation mode is normal

E1L8 = C1L5 & C1L6 & (C1L3 $ !C1L10) # !C1L5 & C1L3 & !C1L6 & C1L10;


--E1L9 is generator_sin:U6|Mux~1318
--operation mode is normal

E1L9 = C1L3 & (C1L10 # C1L5 $ C1L6) # !C1L3 & (C1L5 # C1L6 $ C1L10);


--E1L10 is generator_sin:U6|Mux~1319
--operation mode is normal

E1L10 = C1L8 & (C1L1) # !C1L8 & (C1L1 & !E1L8 # !C1L1 & (E1L9));


--E1L11 is generator_sin:U6|Mux~1320
--operation mode is normal

E1L11 = C1L5 & (C1L3 # !C1L6) # !C1L5 & !C1L3 & C1L6 & C1L10;


--E1L12 is generator_sin:U6|Mux~1322
--operation mode is normal

E1L12 = C1L10 & (C1L6 & !C1L5 # !C1L6 & (C1L1)) # !C1L10 & C1L5 & (C1L6 $ !C1L1);


--E1L13 is generator_sin:U6|Mux~1323
--operation mode is normal

E1L13 = C1L5 & (C1L6 & C1L10 # !C1L6 & (C1L1)) # !C1L5 & (C1L6 & (C1L1) # !C1L6 & C1L10);


--E1L14 is generator_sin:U6|Mux~1324
--operation mode is normal

E1L14 = C1L5 & (C1L1 $ (C1L10 # !C1L3)) # !C1L5 & (C1L1 # C1L3 & C1L10);


--E1L15 is generator_sin:U6|Mux~1325
--operation mode is normal

E1L15 = C1L5 & (C1L10 $ (C1L3 # !C1L1)) # !C1L5 & !C1L3 & !C1L1 & C1L10;


--E1L16 is generator_sin:U6|Mux~1326
--operation mode is normal

E1L16 = C1L1 & (!C1L10 # !C1L3) # !C1L1 & (C1L5 # C1L10);


--E1L17 is generator_sin:U6|Mux~1327
--operation mode is normal

E1L17 = C1L6 & (C1L8) # !C1L6 & (C1L8 & E1L15 # !C1L8 & (E1L16));


--E1L18 is generator_sin:U6|Mux~1328
--operation mode is normal

E1L18 = C1L5 & C1L3 & C1L1 & !C1L10 # !C1L5 & (C1L10 $ (C1L3 & !C1L1));


--E1L19 is generator_sin:U6|Mux~1330
--operation mode is normal

E1L19 = C1L1 & (C1L8 # C1L5 # C1L3);


--E1L20 is generator_sin:U6|Mux~1331
--operation mode is normal

E1L20 = C1L3 & (C1L8 # C1L5);


--E1L21 is generator_sin:U6|Mux~1332
--operation mode is normal

E1L21 = C1L3 & (C1L8 # C1L5);


--E1L22 is generator_sin:U6|Mux~1333
--operation mode is normal

E1L22 = C1L3 & (C1L6 # C1L8 & C1L1) # !C1L3 & (C1L6 & C1L1);


--D1_REG_Q[4] is generator_acc6:U4|REG_Q[4]
--operation mode is arithmetic

D1_REG_Q[4]_carry_eqn = D1L9;
D1_REG_Q[4]_lut_out = D1_REG_Q[4] $ B2_TEMP_Q_0[4] $ !D1_REG_Q[4]_carry_eqn;
D1_REG_Q[4] = DFFEAS(D1_REG_Q[4]_lut_out, CLK, !CLR, , CE, , , , );

--D1L11 is generator_acc6:U4|REG_Q[4]~49
--operation mode is arithmetic

D1L11 = CARRY(D1_REG_Q[4] & (B2_TEMP_Q_0[4] # !D1L9) # !D1_REG_Q[4] & B2_TEMP_Q_0[4] & !D1L9);


--B1_TEMP_Q_0[4] is generator_reg6:U1|TEMP_Q_0[4]
--operation mode is normal

B1_TEMP_Q_0[4]_lut_out = DATA[4];
B1_TEMP_Q_0[4] = DFFEAS(B1_TEMP_Q_0[4]_lut_out, CLK, !CLR, , G2_O, , , , );


--D1_REG_Q[1] is generator_acc6:U4|REG_Q[1]
--operation mode is arithmetic

D1_REG_Q[1]_carry_eqn = D1L3;
D1_REG_Q[1]_lut_out = D1_REG_Q[1] $ B2_TEMP_Q_0[1] $ D1_REG_Q[1]_carry_eqn;
D1_REG_Q[1] = DFFEAS(D1_REG_Q[1]_lut_out, CLK, !CLR, , CE, , , , );

--D1L5 is generator_acc6:U4|REG_Q[1]~53
--operation mode is arithmetic

D1L5 = CARRY(D1_REG_Q[1] & !B2_TEMP_Q_0[1] & !D1L3 # !D1_REG_Q[1] & (!D1L3 # !B2_TEMP_Q_0[1]));


--B1_TEMP_Q_0[1] is generator_reg6:U1|TEMP_Q_0[1]
--operation mode is normal

B1_TEMP_Q_0[1]_lut_out = DATA[1];
B1_TEMP_Q_0[1] = DFFEAS(B1_TEMP_Q_0[1]_lut_out, CLK, !CLR, , G2_O, , , , );


--D1_REG_Q[5] is generator_acc6:U4|REG_Q[5]
--operation mode is normal

D1_REG_Q[5]_carry_eqn = D1L11;
D1_REG_Q[5]_lut_out = D1_REG_Q[5] $ B2_TEMP_Q_0[5] $ D1_REG_Q[5]_carry_eqn;
D1_REG_Q[5] = DFFEAS(D1_REG_Q[5]_lut_out, CLK, !CLR, , CE, , , , );


--B1_TEMP_Q_0[5] is generator_reg6:U1|TEMP_Q_0[5]
--operation mode is normal

B1_TEMP_Q_0[5]_lut_out = DATA[5];
B1_TEMP_Q_0[5] = DFFEAS(B1_TEMP_Q_0[5]_lut_out, CLK, !CLR, , G2_O, , , , );


--D1_REG_Q[2] is generator_acc6:U4|REG_Q[2]
--operation mode is arithmetic

D1_REG_Q[2]_carry_eqn = D1L5;
D1_REG_Q[2]_lut_out = D1_REG_Q[2] $ B2_TEMP_Q_0[2] $ !D1_REG_Q[2]_carry_eqn;
D1_REG_Q[2] = DFFEAS(D1_REG_Q[2]_lut_out, CLK, !CLR, , CE, , , , );

--D1L7 is generator_acc6:U4|REG_Q[2]~61
--operation mode is arithmetic

D1L7 = CARRY(D1_REG_Q[2] & (B2_TEMP_Q_0[2] # !D1L5) # !D1_REG_Q[2] & B2_TEMP_Q_0[2] & !D1L5);


--B1_TEMP_Q_0[2] is generator_reg6:U1|TEMP_Q_0[2]
--operation mode is normal

B1_TEMP_Q_0[2]_lut_out = DATA[2];
B1_TEMP_Q_0[2] = DFFEAS(B1_TEMP_Q_0[2]_lut_out, CLK, !CLR, , G2_O, , , , );


--D1_REG_Q[0] is generator_acc6:U4|REG_Q[0]
--operation mode is arithmetic

D1_REG_Q[0]_lut_out = D1_REG_Q[0] $ B2_TEMP_Q_0[0];
D1_REG_Q[0] = DFFEAS(D1_REG_Q[0]_lut_out, CLK, !CLR, , CE, , , , );

--D1L3 is generator_acc6:U4|REG_Q[0]~65
--operation mode is arithmetic

D1L3 = CARRY(D1_REG_Q[0] & B2_TEMP_Q_0[0]);


--B1_TEMP_Q_0[0] is generator_reg6:U1|TEMP_Q_0[0]
--operation mode is normal

B1_TEMP_Q_0[0]_lut_out = DATA[0];
B1_TEMP_Q_0[0] = DFFEAS(B1_TEMP_Q_0[0]_lut_out, CLK, !CLR, , G2_O, , , , );


--D1_REG_Q[3] is generator_acc6:U4|REG_Q[3]
--operation mode is arithmetic

D1_REG_Q[3]_carry_eqn = D1L7;
D1_REG_Q[3]_lut_out = D1_REG_Q[3] $ B2_TEMP_Q_0[3] $ D1_REG_Q[3]_carry_eqn;
D1_REG_Q[3] = DFFEAS(D1_REG_Q[3]_lut_out, CLK, !CLR, , CE, , , , );

--D1L9 is generator_acc6:U4|REG_Q[3]~69
--operation mode is arithmetic

D1L9 = CARRY(D1_REG_Q[3] & !B2_TEMP_Q_0[3] & !D1L7 # !D1_REG_Q[3] & (!D1L7 # !B2_TEMP_Q_0[3]));


--B1_TEMP_Q_0[3] is generator_reg6:U1|TEMP_Q_0[3]
--operation mode is normal

B1_TEMP_Q_0[3]_lut_out = DATA[3];
B1_TEMP_Q_0[3] = DFFEAS(B1_TEMP_Q_0[3]_lut_out, CLK, !CLR, , G2_O, , , , );


--B2_TEMP_Q_0[4] is generator_reg6:U2|TEMP_Q_0[4]
--operation mode is normal

B2_TEMP_Q_0[4]_lut_out = DATA[4];
B2_TEMP_Q_0[4] = DFFEAS(B2_TEMP_Q_0[4]_lut_out, CLK, !CLR, , G1_O, , , , );


--G2_O is generator_and2:U9|O
--operation mode is normal

G2_O = CE & PR;


--B2_TEMP_Q_0[1] is generator_reg6:U2|TEMP_Q_0[1]
--operation mode is normal

B2_TEMP_Q_0[1]_lut_out = DATA[1];
B2_TEMP_Q_0[1] = DFFEAS(B2_TEMP_Q_0[1]_lut_out, CLK, !CLR, , G1_O, , , , );


--B2_TEMP_Q_0[5] is generator_reg6:U2|TEMP_Q_0[5]
--operation mode is normal

B2_TEMP_Q_0[5]_lut_out = DATA[5];
B2_TEMP_Q_0[5] = DFFEAS(B2_TEMP_Q_0[5]_lut_out, CLK, !CLR, , G1_O, , , , );


--B2_TEMP_Q_0[2] is generator_reg6:U2|TEMP_Q_0[2]
--operation mode is normal

B2_TEMP_Q_0[2]_lut_out = DATA[2];
B2_TEMP_Q_0[2] = DFFEAS(B2_TEMP_Q_0[2]_lut_out, CLK, !CLR, , G1_O, , , , );


--B2_TEMP_Q_0[0] is generator_reg6:U2|TEMP_Q_0[0]
--operation mode is normal

B2_TEMP_Q_0[0]_lut_out = DATA[0];
B2_TEMP_Q_0[0] = DFFEAS(B2_TEMP_Q_0[0]_lut_out, CLK, !CLR, , G1_O, , , , );


--B2_TEMP_Q_0[3] is generator_reg6:U2|TEMP_Q_0[3]
--operation mode is normal

B2_TEMP_Q_0[3]_lut_out = DATA[3];
B2_TEMP_Q_0[3] = DFFEAS(B2_TEMP_Q_0[3]_lut_out, CLK, !CLR, , G1_O, , , , );


--G1_O is generator_and2:U8|O
--operation mode is normal

G1_O = CE & FR;


--E1L23 is generator_sin:U6|Mux~1335
--operation mode is normal

E1L23 = C1L6 & E1L21 & (!C1L5 # !C1L1) # !C1L6 & !E1L21 & (C1L1 # C1L5);


--E1L24 is generator_sin:U6|Mux~1337
--operation mode is normal

E1L24 = E1L20 $ (E1L19 & (C1L6 # !C1L5) # !E1L19 & !C1L5 & C1L6);


--E1L25 is generator_sin:U6|Mux~1339
--operation mode is normal

E1L25 = E1L13 $ (E1L12 & (!C1L6 # !C1L8) # !E1L12 & (C1L6));


--E1L26 is generator_sin:U6|Mux~1341
--operation mode is normal

E1L26 = C1L5 & (C1L1 $ !E1L6) # !C1L5 & (E1L5 $ (C1L1 & E1L6));


--CLK is CLK
--operation mode is input

CLK = INPUT();


--CLR is CLR
--operation mode is input

CLR = INPUT();


--CE is CE
--operation mode is input

CE = INPUT();


--DATA[4] is DATA[4]
--operation mode is input

DATA[4] = INPUT();


--PR is PR
--operation mode is input

PR = INPUT();


--DATA[1] is DATA[1]
--operation mode is input

DATA[1] = INPUT();


--DATA[5] is DATA[5]
--operation mode is input

DATA[5] = INPUT();


--DATA[2] is DATA[2]
--operation mode is input

DATA[2] = INPUT();


--DATA[0] is DATA[0]
--operation mode is input

DATA[0] = INPUT();


--DATA[3] is DATA[3]
--operation mode is input

DATA[3] = INPUT();


--FR is FR
--operation mode is input

FR = INPUT();


--Q[0] is Q[0]
--operation mode is output

Q[0] = OUTPUT(F1_TEMP_Q_1[0]);


--Q[1] is Q[1]
--operation mode is output

Q[1] = OUTPUT(F1_TEMP_Q_1[1]);


--Q[2] is Q[2]
--operation mode is output

Q[2] = OUTPUT(F1_TEMP_Q_1[2]);


--Q[3] is Q[3]
--operation mode is output

Q[3] = OUTPUT(F1_TEMP_Q_1[3]);


--Q[4] is Q[4]
--operation mode is output

Q[4] = OUTPUT(F1_TEMP_Q_1[4]);


--Q[5] is Q[5]
--operation mode is output

Q[5] = OUTPUT(F1_TEMP_Q_1[5]);


--Q[6] is Q[6]
--operation mode is output

Q[6] = OUTPUT(F1_TEMP_Q_1[6]);


--Q[7] is Q[7]
--operation mode is output

Q[7] = OUTPUT(F1_TEMP_Q_1[7]);