half_clk.tan.rpt

这是序列检测器。串行序列产生是指根据时钟和相应的控制信号

; Slack ; Required tsu ; Actual tsu ; From  ; To           ; To Clock ;
+-------+--------------+------------+-------+--------------+----------+
; N/A   ; None         ; 4.200 ns   ; reset ; clk_out~reg0 ; clk_in   ;
+-------+--------------+------------+-------+--------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 13.900 ns  ; clk_out~reg0 ; clk_out ; clk_in     ;
+-------+--------------+------------+--------------+---------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+-------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To           ; To Clock ;
+---------------+-------------+-----------+-------+--------------+----------+
; N/A           ; None        ; -0.100 ns ; reset ; clk_out~reg0 ; clk_in   ;
+---------------+-------------+-----------+-------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Mar 07 09:36:51 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off half_clk -c half_clk
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_in" is an undefined clock
Info: Clock "clk_in" Internal fmax is restricted to 125.0 MHz between source register "clk_out~reg0" and destination register "clk_out~reg0"
    Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.800 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'
            Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'
            Info: Total cell delay = 1.200 ns ( 66.67 % )
            Info: Total interconnect delay = 0.600 ns ( 33.33 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk_in" to destination register is 6.100 ns
                Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_in'
                Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'
                Info: Total cell delay = 3.500 ns ( 57.38 % )
                Info: Total interconnect delay = 2.600 ns ( 42.62 % )
            Info: - Longest clock path from clock "clk_in" to source register is 6.100 ns
                Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_in'
                Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'
                Info: Total cell delay = 3.500 ns ( 57.38 % )
                Info: Total interconnect delay = 2.600 ns ( 42.62 % )
        Info: + Micro clock to output delay of source is 1.100 ns
        Info: + Micro setup delay of destination is 2.500 ns
Info: tsu for register "clk_out~reg0" (data pin = "reset", clock pin = "clk_in") is 4.200 ns
    Info: + Longest pin to register delay is 7.800 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 1; PIN Node = 'reset'
        Info: 2: + IC(2.600 ns) + CELL(1.700 ns) = 7.800 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 5.200 ns ( 66.67 % )
        Info: Total interconnect delay = 2.600 ns ( 33.33 % )
    Info: + Micro setup delay of destination is 2.500 ns
    Info: - Shortest clock path from clock "clk_in" to destination register is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_in'
        Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 3.500 ns ( 57.38 % )
        Info: Total interconnect delay = 2.600 ns ( 42.62 % )
Info: tco from clock "clk_in" to destination pin "clk_out" through register "clk_out~reg0" is 13.900 ns
    Info: + Longest clock path from clock "clk_in" to source register is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_in'
        Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 3.500 ns ( 57.38 % )
        Info: Total interconnect delay = 2.600 ns ( 42.62 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 6.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: 2: + IC(1.600 ns) + CELL(5.100 ns) = 6.700 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 5.100 ns ( 76.12 % )
        Info: Total interconnect delay = 1.600 ns ( 23.88 % )
Info: th for register "clk_out~reg0" (data pin = "reset", clock pin = "clk_in") is -0.100 ns
    Info: + Longest clock path from clock "clk_in" to destination register is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_in'
        Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 3.500 ns ( 57.38 % )
        Info: Total interconnect delay = 2.600 ns ( 42.62 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 7.800 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 1; PIN Node = 'reset'
        Info: 2: + IC(2.600 ns) + CELL(1.700 ns) = 7.800 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 5.200 ns ( 66.67 % )
        Info: Total interconnect delay = 2.600 ns ( 33.33 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Mar 07 09:36:52 2007
    Info: Elapsed time: 00:00:01