📄 half_clk.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_in register register clk_out~reg0 clk_out~reg0 125.0 MHz Internal " "Info: Clock \"clk_in\" Internal fmax is restricted to 125.0 MHz between source register \"clk_out~reg0\" and destination register \"clk_out~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register register " "Info: + Longest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_out~reg0 1 REG LC4_B22 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 1.800 ns clk_out~reg0 2 REG LC4_B22 2 " "Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk_out~reg0 clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 66.67 % ) " "Info: Total cell delay = 1.200 ns ( 66.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 33.33 % ) " "Info: Total interconnect delay = 0.600 ns ( 33.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk_out~reg0 clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk_out~reg0 clk_out~reg0 } { 0.000ns 0.600ns } { 0.000ns 1.200ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 6.100 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk_in 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_in'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 6.100 ns clk_out~reg0 2 REG LC4_B22 2 " "Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 57.38 % ) " "Info: Total cell delay = 3.500 ns ( 57.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 42.62 % ) " "Info: Total interconnect delay = 2.600 ns ( 42.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 6.100 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk_in 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_in'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 6.100 ns clk_out~reg0 2 REG LC4_B22 2 " "Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 57.38 % ) " "Info: Total cell delay = 3.500 ns ( 57.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 42.62 % ) " "Info: Total interconnect delay = 2.600 ns ( 42.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk_out~reg0 clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk_out~reg0 clk_out~reg0 } { 0.000ns 0.600ns } { 0.000ns 1.200ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { clk_out~reg0 } { } { } } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "clk_out~reg0 reset clk_in 4.200 ns register " "Info: tsu for register \"clk_out~reg0\" (data pin = \"reset\", clock pin = \"clk_in\") is 4.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.800 ns + Longest pin register " "Info: + Longest pin to register delay is 7.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns reset 1 PIN PIN_19 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 1; PIN Node = 'reset'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.700 ns) 7.800 ns clk_out~reg0 2 REG LC4_B22 2 " "Info: 2: + IC(2.600 ns) + CELL(1.700 ns) = 7.800 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.300 ns" { reset clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 66.67 % ) " "Info: Total cell delay = 5.200 ns ( 66.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 33.33 % ) " "Info: Total interconnect delay = 2.600 ns ( 33.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.800 ns" { reset clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.800 ns" { reset reset~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 1.700ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 6.100 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_in\" to destination register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk_in 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_in'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 6.100 ns clk_out~reg0 2 REG LC4_B22 2 " "Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 57.38 % ) " "Info: Total cell delay = 3.500 ns ( 57.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 42.62 % ) " "Info: Total interconnect delay = 2.600 ns ( 42.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.800 ns" { reset clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.800 ns" { reset reset~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 1.700ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in clk_out clk_out~reg0 13.900 ns register " "Info: tco from clock \"clk_in\" to destination pin \"clk_out\" through register \"clk_out~reg0\" is 13.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 6.100 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to source register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk_in 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_in'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 6.100 ns clk_out~reg0 2 REG LC4_B22 2 " "Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 57.38 % ) " "Info: Total cell delay = 3.500 ns ( 57.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 42.62 % ) " "Info: Total interconnect delay = 2.600 ns ( 42.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.700 ns + Longest register pin " "Info: + Longest register to pin delay is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_out~reg0 1 REG LC4_B22 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(5.100 ns) 6.700 ns clk_out 2 PIN PIN_20 0 " "Info: 2: + IC(1.600 ns) + CELL(5.100 ns) = 6.700 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'clk_out'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 76.12 % ) " "Info: Total cell delay = 5.100 ns ( 76.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 23.88 % ) " "Info: Total interconnect delay = 1.600 ns ( 23.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.700 ns" { clk_out~reg0 clk_out } { 0.000ns 1.600ns } { 0.000ns 5.100ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.700 ns" { clk_out~reg0 clk_out } { 0.000ns 1.600ns } { 0.000ns 5.100ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "clk_out~reg0 reset clk_in -0.100 ns register " "Info: th for register \"clk_out~reg0\" (data pin = \"reset\", clock pin = \"clk_in\") is -0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 6.100 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to destination register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk_in 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_in'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 6.100 ns clk_out~reg0 2 REG LC4_B22 2 " "Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 57.38 % ) " "Info: Total cell delay = 3.500 ns ( 57.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 42.62 % ) " "Info: Total interconnect delay = 2.600 ns ( 42.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" { } { { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns reset 1 PIN PIN_19 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 1; PIN Node = 'reset'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.700 ns) 7.800 ns clk_out~reg0 2 REG LC4_B22 2 " "Info: 2: + IC(2.600 ns) + CELL(1.700 ns) = 7.800 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'clk_out~reg0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.300 ns" { reset clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/altera/x/half_clk.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 66.67 % ) " "Info: Total cell delay = 5.200 ns ( 66.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 33.33 % ) " "Info: Total interconnect delay = 2.600 ns ( 33.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.800 ns" { reset clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.800 ns" { reset reset~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 1.700ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 0.000ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.800 ns" { reset clk_out~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.800 ns" { reset reset~out clk_out~reg0 } { 0.000ns 0.000ns 2.600ns } { 0.000ns 3.500ns 1.700ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 07 09:36:52 2007 " "Info: Processing ended: Wed Mar 07 09:36:52 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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