half_clk.map.summary

这是序列检测器。串行序列产生是指根据时钟和相应的控制信号

Analysis & Synthesis Status : Successful - Wed Mar 07 09:36:23 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : half_clk
Top-level Entity Name : half_clk
Family : FLEX10K
Total logic elements : 1
Total pins : 3
Total memory bits : 0