half_clk.fit.summary

来自「这是序列检测器。串行序列产生是指根据时钟和相应的控制信号」· SUMMARY 代码 · 共 11 行

Fitter Status : Successful - Wed Mar 07 09:36:39 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : half_clk
Top-level Entity Name : half_clk
Family : FLEX10K
Device : EPF10K10TC144-4
Timing Models : Final
Total logic elements : 1 / 576 ( < 1 % )
Total pins : 3 / 102 ( 3 % )
Total memory bits : 0 / 6,144 ( 0 % )