scram_encode.v

来自「LAPS协议的设计与实现」· Verilog 代码 · 共 43 行

module scram_encode(
                        //input
                        clk,
                        rst_n,
                        enframe_data,
                        //output
                        scram_data
                        );
//=========================================================//
//============	I/O direction  =============================//
//=========================================================//
input        clk;
input        rst_n;
input  [7:0] enframe_data;
output [7:0] scram_data;
//=========================================================//
//=================	I/O Type  =============================//
//=========================================================//
wire [7:0] scram_data;

//=========================================================//
//============	Internal Signals  ==========================//
//=========================================================//
wire [7:0]  scram_data_buffer;
reg  [43:1] scram_poly;

//==========================================================//
//====================	Process  ============================//
//==========================================================//
assign scram_data = scram_data_buffer;
assign scram_data_buffer = enframe_data^{scram_poly[1],scram_poly[2],scram_poly[3],
                          scram_poly[4],scram_poly[5],scram_poly[6],scram_poly[7],scram_poly[8]};

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)   scram_poly <= 43'd0;
    else         scram_poly <= {scram_data_buffer[0],scram_data_buffer[1],
                                scram_data_buffer[2],scram_data_buffer[3],
                                scram_data_buffer[4],scram_data_buffer[5],
                                scram_data_buffer[6],scram_data_buffer[7],
                                scram_poly[43:9]};
end

endmodule