data_receive.v

来自「LAPS协议的设计与实现」· Verilog 代码 · 共 98 行

module data_receive(
                    //input
                    clk,
                    rst_n,
                    Tdata,
                    Tsop,
                    Teop,
                    //output
                    Tdata_out,
                    fifo_trans_wrreq,
                    bytes_data_num
                    );
//=========================================================//
//============	I/O direction  =============================//
//=========================================================//
input        clk;
input        rst_n;
input [7:0]  Tdata;
input        Tsop;
input        Teop;
output[7:0]  Tdata_out;
output       fifo_trans_wrreq;
output[10:0] bytes_data_num;	
//=========================================================//
//=================	I/O Type  =============================//
//=========================================================//
reg  [7:0]  Tdata_out;
reg         fifo_trans_wrreq;
reg [10:0]  bytes_data_num;	
//=========================================================//
//============	Internal Signals  ==========================//
//=========================================================//
reg  [10:0]  bytes_data_cnt;
reg          flag_cnt;
reg          trans_data_end;
//==========================================================//
//====================	Process  ============================//
//==========================================================//
//the number of trans data,actually is num-1
always @(posedge clk or negedge rst_n)  begin
	 if(!rst_n)  begin 
	    	bytes_data_cnt<=11'd0;
		  flag_cnt<=1'b0;
	 end
	 else  begin
		  if(Tsop)  begin 
			   bytes_data_cnt<=11'd0;
				flag_cnt<=1'b1;
		  end
		  else begin
				if(flag_cnt) begin
            				bytes_data_cnt<=bytes_data_cnt+11'd1;
            				flag_cnt<=flag_cnt;
        				end
				else if(Teop) begin
				    bytes_data_cnt<=bytes_data_cnt;
                flag_cnt<=1'd0;
            end
            else  begin
                bytes_data_cnt<=bytes_data_cnt;
                flag_cnt<=flag_cnt;
            end
      		end
  	 end
end
//fifo_trans_wrreq
always @(posedge clk or negedge rst_n)  begin
	 if(!rst_n)  fifo_trans_wrreq <= 1'b0;
	 else  begin
	     if(Tsop)                fifo_trans_wrreq <= 1'b1;
	     else if(trans_data_end) fifo_trans_wrreq <= 1'b0;
	     else                    fifo_trans_wrreq <= fifo_trans_wrreq;
	 end
end
//bytes_data_num
always @(posedge clk or negedge rst_n)  begin
	 if(!rst_n)  bytes_data_num <= 11'd0;
	 else  begin
	     if(fifo_trans_wrreq)  bytes_data_num <= bytes_data_cnt;
	     else                  bytes_data_num <= bytes_data_num;
	 end
end
//all trans data 
always @(posedge clk or negedge rst_n)  begin
	 if(!rst_n)  trans_data_end <= 1'b0;
	 else  begin
	     if(Tsop)      trans_data_end <= 1'b0;
	     else if(Teop) trans_data_end <= 1'b1;
	     else          trans_data_end <= trans_data_end;
    end
end
//Tdata_out
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)  Tdata_out <= 8'd0;
    else        Tdata_out <= Tdata;
end

endmodule