scram_decode.v

来自「LAPS协议的设计与实现」· Verilog 代码 · 共 44 行

module scram_decode(
                        //input
                        clk,
                        rst_n,
                        scram_data_in,
                        //output
                        frame_data
                        );
//=========================================================//
//============	I/O direction  =============================//
//=========================================================//
input        clk;
input        rst_n;
input  [7:0] scram_data_in;
output [7:0] frame_data;
//=========================================================//
//=================	I/O Type  =============================//
//=========================================================//
wire [7:0] frame_data;

//=========================================================//
//============	Internal Signals  ==========================//
//=========================================================//
wire [7:0]  frame_data_buffer;
reg  [43:1] unscram_poly;

//==========================================================//
//====================	Process  ============================//
//==========================================================//
assign frame_data = frame_data_buffer;
assign frame_data_buffer = scram_data_in^{unscram_poly[1],unscram_poly[2],unscram_poly[3],
                          unscram_poly[4],unscram_poly[5],unscram_poly[6],unscram_poly[7],
                          unscram_poly[8]};

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)   unscram_poly <= 43'd0;
    else         unscram_poly <= {scram_data_in[0],scram_data_in[1],
                                scram_data_in[2],scram_data_in[3],
                                scram_data_in[4],scram_data_in[5],
                                scram_data_in[6],scram_data_in[7],
                                unscram_poly[43:9]};
end

endmodule