enframe.v

LAPS协议的设计与实现

module  enframe(
                //input
                clk,
                rst_n,
                Tsop,
                bytes_data_num,
                Tdata_to_enframe,
                //output
                fifo_trans_rdreq,
                Dout,
                Tenb
                );
//=========================================================//
//============	I/O direction  =============================//
//=========================================================//
input        clk;
input        rst_n;
input        Tsop;
input [10:0] bytes_data_num;
input [7:0]  Tdata_to_enframe;
output       fifo_trans_rdreq;
output[7:0]  Dout;
output       Tenb;

//=========================================================//
//=================	I/O Type  =============================//
//=========================================================//
reg         fifo_trans_rdreq;
reg  [7:0]  Dout;
reg         Tenb;
//=========================================================//
//============	Internal Signals  ==========================//
//=========================================================//
reg         sapi_cnt;
reg  [10:0] data_cnt;
reg  [1:0]  data_type;
reg         tag1;//for 2-cycle
reg         tag2;
reg         crc_added;
wire [15:0] LUT[15:0];		
reg  [1:0]  tag_crc;
reg         first_crc;
reg  [15:0] buffer_crc;
reg  [15:0] reg_crc;

reg  [2:0]  current_state;
reg  [2:0]  next_state;
//==========================================================//
//============	Internal Nets Assignments ===================//
//==========================================================//
assign      LUT[0] = 16'h1021,	//Look Up Table for crc		 
			   LUT[1] = 16'h2042,
      	     LUT[2] = 16'h4084,
				LUT[3] = 16'h8108,
      		    LUT[4] = 16'h1231,
				LUT[5] = 16'h2462,
            LUT[6] = 16'h48C4,
            LUT[7] = 16'h9188,
         			LUT[8] = 16'h3331,
           	LUT[9] = 16'h6662,
				LUT[10]= 16'hCCC4,
				LUT[11]= 16'h89A9,
				LUT[12]= 16'h0373,
				LUT[13]= 16'h06E6,
				LUT[14]= 16'h0DCC,
				LUT[15]= 16'h1B98; 
//=========================================================//
//============	Parameters Define  =========================//
//=========================================================//
parameter IDLE  = 3'b000,
          ADDR  = 3'b001,
          CONTR = 3'b010,
          SAPI  = 3'b011,
          DATA  = 3'b100,
          CRC   = 3'b101;
//==========================================================//
//====================	Process  ============================//
//==========================================================//
//main state machine
//State transit
always @ (posedge clk or negedge rst_n)  begin
  if (!rst_n)  current_state <= IDLE;
  else         current_state <= next_state;
end
//state generation
always @ (*)  begin
    if(!rst_n)     next_state <= IDLE;
    else  begin
        case(current_state)
        IDLE:  begin
            if(Tsop)		next_state <= ADDR;
            else      next_state <= IDLE;
        end
        ADDR:  next_state <= CONTR;
        CONTR: next_state <= SAPI;
        SAPI:  begin
            if(sapi_cnt) next_state <= DATA;
            else         next_state <= SAPI;
        end 
        DATA:  begin
            if(data_cnt==bytes_data_num+1) next_state <= CRC;
            else                           next_state <= DATA;
        end
        CRC:  begin
            if(crc_added)  next_state <= IDLE;
            else           next_state <= CRC;
        end
        default: next_state <= IDLE; 
        endcase
    end
end
//cnt generation
//sapi_cnt         
always @ (posedge clk or negedge rst_n)  begin
    if(!rst_n)   sapi_cnt<=1'b0;
    else  begin
        if(current_state==SAPI) sapi_cnt <= ~sapi_cnt;
        else                    sapi_cnt <= 1'b0;
    end
end 
//data_cnt
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)  data_cnt <= 11'd0;
    else  begin
		  if(current_state==DATA)  begin
		      if(data_cnt==bytes_data_num+1)  data_cnt <= 11'd0;
			   else  begin 	   
					 case(data_type)
					 2'b00:  data_cnt <= data_cnt + 11'd1;
					 2'b01:  begin
					     if(!tag1) data_cnt <= data_cnt + 11'd1;
						  else   		 data_cnt <= data_cnt;						
				    end
					 2'b10:  begin 
					     if(!tag2) data_cnt <= data_cnt + 11'd1;
						  else   		 data_cnt <= data_cnt;						
				    end
					 default:;
					 endcase											
				end
		  end
		  else  data_cnt <= 11'd0;
	 end
end
//fifo_trans_rdreq
always@(*)  begin
    if(!rst_n)    fifo_trans_rdreq = 1'b0;
    else  begin
        if(current_state==SAPI && sapi_cnt) fifo_trans_rdreq = 1'b1;
	     else if(current_state==DATA) begin
	         if(data_cnt==bytes_data_num+1)  fifo_trans_rdreq = 1'b0;
	         else  begin
	             case(data_type)
                2'b01:  begin 
                    if(tag1) fifo_trans_rdreq = 1'b1;
                    else     fifo_trans_rdreq = 1'b0;
	             end
	             2'b10:  begin 
                    if(tag2) fifo_trans_rdreq = 1'b1;
                    else     fifo_trans_rdreq = 1'b0;
                end
                default: fifo_trans_rdreq = 1'b1;
                endcase
            end
        end
        else  fifo_trans_rdreq = 1'b0;
    end
end
//data_type
always@(*)  begin
	 case(Tdata_to_enframe)
	 8'h7e:   data_type = 2'b01;
    8'h7d:   data_type = 2'b10;
	 default: data_type = 2'b00;
    endcase
end
//Dout[7:0]
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)  begin
        Dout      <= 8'h7e;
        tag1      <= 1'b0;
        tag2      <= 1'b0;
        tag_crc   <= 2'b00;
        first_crc <= 1'b1;
    end
	 else  begin
		  case(current_state)
		  IDLE:  Dout<=8'h7e;					
		  ADDR:  Dout<=8'h04;						
		  CONTR:	Dout<=8'h03;			
		  SAPI:  begin 
				if(!sapi_cnt)		Dout<=8'hfe;
				else   					Dout<=8'h01;													
		  end
		  DATA:  begin				
				if(data_cnt==bytes_data_num+1)  begin
				    first_crc <= 1'b1; //the higher 8-bit
					 if(reg_crc[15:8]==8'h7e)  begin
					     Dout    <= 8'h7d;
					     tag_crc <= 2'b01;
					 end
					 else if(reg_crc[15:8]==8'h7d) begin
					     Dout    <= 8'h7d;
					     tag_crc <= 2'b10;
					 end
					 else  begin
					     Dout<=reg_crc[15:8];
					     tag_crc <= 2'b00;
					 end
		      end
		      else  begin 	   
					 case(data_type)
					 2'b00: Dout <= Tdata_to_enframe;
					 2'b01:  begin
					     tag1 <= ~tag1;
					   	 if(!tag1) Dout<=8'h7d;
						  else   			Dout<=8'h5e;								
				    end
					 2'b10:  begin 
					     tag2 <= ~tag2;
				      		if(!tag2) Dout<=8'h7d;
						  else      Dout<=8'h5d;
					 end						
					 default:;
					 endcase											
				end
		  end
		  CRC:  begin
		      case (tag_crc) //7e,7d or normal data
				2'b00: 	begin
				    first_crc <= 1'b0;//the lower 8-bit
				    if(reg_crc[7:0]==8'h7e)  begin
				        Dout<=8'h7d;
				        tag_crc <= 2'b01;
				    end
				    else if(reg_crc[7:0]==8'h7d)  begin
				        Dout<=8'h7d;
				        tag_crc <= 2'b10;
				    end
				    else		Dout <= reg_crc[7:0]; 
			   end
				2'b01:  begin
				    Dout<= 8'h5e;
				    if(first_crc) tag_crc   <= 2'b00;
				end
				2'b10:  begin
				    Dout<= 8'h5d;
				    if(first_crc) tag_crc   <= 2'b00;
				end
			   default:;
				endcase
		  end	   
		  endcase
	 end
end
//crc_added
always @(*)  begin
    if(!rst_n) crc_added <= 1'b0;
	 else  begin
		  if(current_state==IDLE)  crc_added = 1'b0;
		  else if(current_state==CRC)  begin
		      case (tag_crc)
				2'b00: 	begin
				    if(reg_crc[7:0]!=8'h7e&&reg_crc[7:0]!=8'h7d) 
				          crc_added = 1'b1;
				    else  crc_added = 1'b0; 
			   end
				2'b01:  begin
				    if(!first_crc) crc_added = 1'b1;
				    else           crc_added = 1'b0;
				end
				2'b10:  begin
				    if(!first_crc) crc_added = 1'b1;
				    else           crc_added = 1'b0;
				end
			   default:;
				endcase
		  end
	     else   crc_added = 1'b0;
	 end
end
//Tenb,point that if could be transfered
always @ (posedge clk or negedge rst_n)  begin
    if(!rst_n)     Tenb <= 1'b1;
    else  begin
        case(current_state)
        SAPI:  if(sapi_cnt) Tenb <= 1'b0;
        DATA:  begin
            if(data_cnt==bytes_data_num+1)  Tenb <= 1'b1;
            else                            Tenb <= 1'b0;
        end
        default: Tenb <= 1'b1; 
        endcase
    end
end

//====================	CRC ==========================//
//buffer_crc
always @(*)  begin
     if(!rst_n)  buffer_crc = 16'd0;
	 else  begin
	     case(current_state)
	     ADDR:	 buffer_crc = reg_crc[7:0]^8'h04;						
	     CONTR:  buffer_crc = reg_crc[7:0]^8'h03;			
	     SAPI:  begin 
		     if(!sapi_cnt)  buffer_crc = reg_crc[7:0]^8'hfe;
		     else           buffer_crc = reg_crc[7:0]^8'h01;													
	     end
	     DATA:  begin
	         if(data_cnt==bytes_data_num+1)  buffer_crc = buffer_crc;
	         else  begin
	             case(data_type)
	             2'b00:  buffer_crc = reg_crc[7:0]^Tdata_to_enframe;
                 2'b01:  begin 
                     if(!tag1) buffer_crc = reg_crc[7:0]^Tdata_to_enframe;
                     else      buffer_crc = buffer_crc; 
	             end
	             2'b10:  begin 
                     if(!tag2) buffer_crc = reg_crc[7:0]^Tdata_to_enframe;
                     else      buffer_crc = buffer_crc; 
                 end
                 default: buffer_crc = buffer_crc;
                 endcase
             end
         end
         default: buffer_crc = buffer_crc;
	     endcase
	end
end
//reg_crc
always @(posedge clk or negedge rst_n)  begin
	 if(!rst_n)  reg_crc  <= 16'hffff;
	 else	 begin 
	     case(current_state)
	     ADDR,
	     CONTR,
	     SAPI: reg_crc <= f(LUT[0],buffer_crc[0])^f(LUT[1],buffer_crc[1])^
	                    f(LUT[2],buffer_crc[2])^f(LUT[3],buffer_crc[3])^
	                    f(LUT[4],buffer_crc[4])^f(LUT[5],buffer_crc[5])^
							  f(LUT[6],buffer_crc[6])^f(LUT[7],buffer_crc[7])^
							  f(LUT[8],reg_crc[8])^f(LUT[9],reg_crc[9])^
							  f(LUT[10],reg_crc[10])^f(LUT[11],reg_crc[11])^
							  f(LUT[12],reg_crc[12])^f(LUT[13],reg_crc[13])^
							  f(LUT[14],reg_crc[14])^f(LUT[15],reg_crc[15]);
	     DATA:  begin
		      if(fifo_trans_rdreq)							
	         reg_crc <= f(LUT[0],buffer_crc[0])^f(LUT[1],buffer_crc[1])^
	                    f(LUT[2],buffer_crc[2])^f(LUT[3],buffer_crc[3])^
	                    f(LUT[4],buffer_crc[4])^f(LUT[5],buffer_crc[5])^
							  f(LUT[6],buffer_crc[6])^f(LUT[7],buffer_crc[7])^
							  f(LUT[8],reg_crc[8])^f(LUT[9],reg_crc[9])^
							  f(LUT[10],reg_crc[10])^f(LUT[11],reg_crc[11])^
							  f(LUT[12],reg_crc[12])^f(LUT[13],reg_crc[13])^
							  f(LUT[14],reg_crc[14])^f(LUT[15],reg_crc[15]);
	     end
	     CRC:  begin
	         if(crc_added) reg_crc <= 16'hffff;
	         else          reg_crc <= reg_crc;
	     end
        default: reg_crc <= reg_crc;
        endcase
    end
end
//function for predigest  	
function [15:0] f;
input[15:0] a;
input       b;
	 if(b)  f = a;
	 else   f = 16'd0;
endfunction

endmodule