data_trans.v

LAPS协议的设计与实现

module data_trans(
                  //input
                  clk,
                  rst_n,
                  data_deframe,
                  deframe_eop,
                  bytes_data_num,
                  fifo_receive_empty,
                  //output
                  Rdata,
                  Rsop,
                  Reop,
                  Renb,
                  fifo_receive_rdreq
                  );
//=========================================================//
//============	I/O direction  =============================//
//=========================================================//
input        clk;
input        rst_n;
input [7:0]  data_deframe;
input        deframe_eop;
input [10:0] bytes_data_num;
input        fifo_receive_empty;
output[7:0]  Rdata;
output       Rsop;
output       Reop;
output       Renb;
output       fifo_receive_rdreq;
//=========================================================//
//=================	I/O Type  =============================//
//=========================================================//
reg  [7:0]  Rdata;
reg         Rsop;
reg         Reop;
reg         Renb;
reg         fifo_receive_rdreq;
//=========================================================//
//============	Internal Signals  ==========================//
//=========================================================//
reg          data_valid;
reg  [10:0]  data_cnt;
reg  [4:0]   flag_cnt;
wire [15:0]  LUT[15:0];		
reg  [15:0]  reg_crc_frame;
reg  [15:0]  reg_crc;
reg  [15:0]  buffer_crc;
//==========================================================//
//============	Internal Nets Assignments ===================//
//==========================================================//
assign      LUT[0] = 16'h1021,	//Look Up Table for crc		 
			   LUT[1] = 16'h2042,
      	     LUT[2] = 16'h4084,
				LUT[3] = 16'h8108,
      		    LUT[4] = 16'h1231,
				LUT[5] = 16'h2462,
            LUT[6] = 16'h48C4,
            LUT[7] = 16'h9188,
         			LUT[8] = 16'h3331,
           	LUT[9] = 16'h6662,
				LUT[10]= 16'hCCC4,
				LUT[11]= 16'h89A9,
				LUT[12]= 16'h0373,
				LUT[13]= 16'h06E6,
				LUT[14]= 16'h0DCC,
				LUT[15]= 16'h1B98; 

//==========================================================//
//====================	Process  ============================//
//==========================================================//
//Rsop
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)                    Rsop <= 1'b0;
    else if((data_deframe!=8'h7e)&&(flag_cnt>=5'd4))  
                                  Rsop <= 1'b1;
    else                          Rsop <= 1'b0;
end
//flag_cnt
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)    flag_cnt <= 1'b0;
    else if(data_deframe==8'h7e)  flag_cnt <= flag_cnt+1'b1;
    else                          flag_cnt <= 1'b0;
end
//Reop
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)    Reop <= 1'b0;
    else if(data_cnt==bytes_data_num+11'd2)  Reop <= 1'b1;
    else                                     Reop <= 1'b0;
end
//data_valid
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)        data_valid <= 1'b0;
    else if((data_deframe!=8'h7e)&&(flag_cnt>=5'd4))
                      data_valid <= 1'b1;
    else if(Reop)     data_valid <= 1'b0;              
end
//data_cnt
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)     data_cnt <= 11'd0;
    else begin
        if(Rsop) data_cnt <= data_cnt + 11'd1;
        else if(data_cnt==bytes_data_num+11'd5)  
            data_cnt <= 11'd0;
        else if(data_cnt!=11'd0) 
            data_cnt <= data_cnt + 11'd1;   
    end 
end
//fifo_receive_rdreq
always @(posedge clk or negedge rst_n)  begin
	 if(!rst_n)  fifo_receive_rdreq <= 1'b0;
	 else  begin
	     if(deframe_eop)             fifo_receive_rdreq <= 1'b1;
	     else if(fifo_receive_empty) fifo_receive_rdreq <= 1'b0;
	     else     fifo_receive_rdreq <= fifo_receive_rdreq;
	 end
end
//Rdata
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)  Rdata <= 8'd0;
    else        Rdata <= data_deframe;
end
//Renb
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)  Renb <= 1'b0;
    else if(data_cnt==bytes_data_num+11'd5)	  
         Renb <= (reg_crc_frame==reg_crc);
    else Renb <= 1'b0;
end
//====================	CRC ==========================//
//reg_crc_frame
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)  reg_crc_frame <= 16'd0;
    else if(data_cnt==bytes_data_num+11'd3) reg_crc_frame[15:8]<= data_deframe;
	 else if(data_cnt==bytes_data_num+11'd4)	reg_crc_frame[7:0] <= data_deframe;
end
//buffer_crc
always @(*)  begin
     if(!rst_n)           buffer_crc = 16'd0;  
	 else if(data_valid)  buffer_crc = reg_crc[7:0]^Rdata;
     else                 buffer_crc = buffer_crc;
end
//reg_crc
always @(posedge clk or negedge rst_n)  begin
	 if(!rst_n)  reg_crc <= 16'hffff;
	 else  begin 
	     if(data_valid)  begin								
	         reg_crc <= f(LUT[0],buffer_crc[0]) ^ f(LUT[1],buffer_crc[1])^
	                    f(LUT[2],buffer_crc[2]) ^ f(LUT[3],buffer_crc[3])^
	                    f(LUT[4],buffer_crc[4]) ^ f(LUT[5],buffer_crc[5])^
							  f(LUT[6],buffer_crc[6]) ^ f(LUT[7],buffer_crc[7])^
							  f(LUT[8],reg_crc[8]) ^ f(LUT[9],reg_crc[9])^
							  f(LUT[10],reg_crc[10]) ^ f(LUT[11],reg_crc[11])^
							  f(LUT[12],reg_crc[12]) ^ f(LUT[13],reg_crc[13])^
							  f(LUT[14],reg_crc[14]) ^ f(LUT[15],reg_crc[15]);
		
		  end
	 end
end
//function for predigest  	
function [15:0] f;
input[15:0] a;
input       b;
	 if(b)  f = a;
	 else   f = 16'd0;
endfunction

endmodule