deframe.v

LAPS协议的设计与实现

module  deframe(
                //input
                clk,
                rst_n,
                Din,
                //output
                bytes_data_num,
                data_from_laps,
                fifo_receive_wrreq,
                deframe_eop
                );
//=========================================================//
//============	I/O direction  =============================//
//=========================================================//
input        clk;
input        rst_n;
input  [7:0] Din;
output [10:0]bytes_data_num;
output [7:0] data_from_laps;
output       fifo_receive_wrreq;
output       deframe_eop;
//=========================================================//
//=================	I/O Type  =============================//
//=========================================================//
reg [10:0]bytes_data_num;
reg [7:0] data_from_laps;
reg       fifo_receive_wrreq;
reg       deframe_eop;
//=========================================================//
//============	Internal Signals  ==========================//
//=========================================================//
reg         Rsop;
reg         sapi_cnt;
reg  [10:0] data_cnt;
reg  [7:0]  data_buffer;
reg  [4:0]  flag_cnt; //min flag num is 4
reg         data_tag1;
reg         data_tag2;

reg  [2:0]  current_state;
reg  [2:0]  next_state;
//=========================================================//
//============	Parameters Define  =========================//
//=========================================================//
parameter IDLE  = 3'b000,
          ADDR  = 3'b001,
          CONTR = 3'b010,
          SAPI  = 3'b011,
          DATA  = 3'b100,
          CRC   = 3'b101;

//==========================================================//
//====================	Process  ============================//
//==========================================================//
//data_buffer
always @ (posedge clk or negedge rst_n)  begin
  if (!rst_n)  data_buffer <= 8'd0;
  else         data_buffer <= Din;
end
//main state machine
//State transit
always @ (posedge clk or negedge rst_n)  begin
  if (!rst_n)  current_state <= IDLE;
  else         current_state <= next_state;
end
//state generation
always @ (*)  begin
    if(!rst_n)    next_state <= IDLE;
    else  begin
        case(current_state)
            IDLE:  begin 
					 if(Rsop)  next_state <= ADDR;
					 else      next_state <= IDLE;
				end
				ADDR:  next_state <= CONTR;
				CONTR:	next_state <= SAPI;
				SAPI:  begin 
					 if(sapi_cnt)  next_state <= DATA;
					 else          next_state <= SAPI;
				end
				DATA:  begin
				  	 if(Din==8'h7e) next_state <= CRC;
					 else           next_state <= DATA;
				end
				CRC:	 next_state <= IDLE;
				default: next_state <= IDLE;
		  endcase
	 end
end
//Rsop
always @ (posedge clk or negedge rst_n)  begin
    if (!rst_n)  Rsop<= 1'b0;
    else  if(current_state==IDLE)  begin
        if(Din!=8'h7e && flag_cnt >= 5'd4)  Rsop <= 1'b1;
        else                                Rsop <= 1'b0;
    end
    else                                    Rsop <= 1'b0;
end
//cnt generation
//sapi_cnt         
always @ (posedge clk or negedge rst_n)  begin
    if(!rst_n)   sapi_cnt<=1'b0;
    else  begin
        if(current_state==SAPI) sapi_cnt <= ~sapi_cnt;
        else                    sapi_cnt <= 1'b0;
    end
end	
//flag_cnt
always @ (posedge clk or negedge rst_n)  begin
    if(!rst_n)   flag_cnt<=5'd4;
    else  begin
        if(current_state==IDLE) flag_cnt <= flag_cnt + 5'b1;
        else if(current_state==CRC)  flag_cnt<=5'b1;
        else if(current_state==ADDR) flag_cnt<=5'b0;
    end
end	
//data_cnt
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)  data_cnt <= 11'd0;
    else  begin
        if(current_state==DATA)  begin
		      if((data_buffer==8'h7d)&&(Din==8'h5e))	     data_cnt <= data_cnt;
			   else if((data_buffer==8'h7d)&&(Din==8'h5d)) data_cnt <= data_cnt;	
			   else    data_cnt <= data_cnt + 11'd1;					
		  end
		  else  data_cnt <= 11'd0;
	 end
end
//bytes_data_num
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)  bytes_data_num <= 11'd0;
    else  begin
		  if(current_state==CRC)  bytes_data_num <= data_cnt - 11'd1;
		  else                    bytes_data_num <= bytes_data_num;
	 end
end

//data_from_laps
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)  begin
        data_from_laps  <= 8'h7e;
        data_tag1       <= 1'b0;
        data_tag2       <= 1'b0;
    end
	 else  begin
		  case(current_state)
		  IDLE:  begin
		      data_tag1 <= 1'b0;
            data_tag2 <= 1'b0;
            if(Rsop) 	data_from_laps <= 8'h04;	
       	end	
		  ADDR:  data_from_laps <= 8'h03;				
		  CONTR: data_from_laps <= 8'hfe;			
		  SAPI:  begin
		      if(!sapi_cnt) data_from_laps <= 8'h01;
		      else          data_from_laps <= data_buffer;
		  end        			
		  DATA:  begin				
				if((data_buffer==8'h7d)&&(Din==8'h5e))  begin
			       data_tag1 <= ~data_tag1;
					 data_from_laps <= 8'h7e;
			   end
			   else if((data_buffer==8'h7d)&&(Din==8'h5d)) begin
					 data_tag2 <= ~data_tag2;
					 data_from_laps <= 8'h7d;
			   end
			   else  begin
			       data_tag1 <= 1'b0;
			       data_tag2 <= 1'b0;
			       data_from_laps <= data_buffer;
			   end
		  end
		  default: data_from_laps <= 8'h7e;
		  endcase
   	end	   
end
//fifo_receive_wrreq
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)    fifo_receive_wrreq <= 1'b0;
    else  begin
        case(current_state)
		  DATA:  begin
	         if(data_tag1||data_tag2)  fifo_receive_wrreq <= 1'b0;
	         else                      fifo_receive_wrreq <= 1'b1;
	     end
	     default:  fifo_receive_wrreq <= 1'b1;//8'h7e will be more than 4 
	     endcase
	  end 
end
//deframe_eop
always @(posedge clk or negedge rst_n)  begin
    if(!rst_n)  deframe_eop <= 1'b0;
    else  begin
		  if(current_state==CRC)  deframe_eop <= 1'b1;
		  else                    deframe_eop <= 1'b0;
	 end
end

endmodule