📄 rom.rpt
字号:
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
73 - - - 01 INPUT 0 0 0 32 addressin0
120 - - - 08 INPUT 0 0 0 32 addressin1
125 - - - -- INPUT 0 0 0 32 addressin2
55 - - - -- INPUT 0 0 0 32 addressin3
126 - - - -- INPUT 0 0 0 32 addressin4
124 - - - -- INPUT 0 0 0 32 addressin5
56 - - - -- INPUT 0 0 0 32 addressin6
54 - - - -- INPUT 0 0 0 32 addressin7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\project\cpu\rom.rpt
rom
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - E -- OUTPUT 0 1 0 0 c0
33 - - F -- OUTPUT 0 1 0 0 c1
80 - - F -- OUTPUT 0 1 0 0 c2
32 - - F -- OUTPUT 0 1 0 0 c3
78 - - F -- OUTPUT 0 1 0 0 c4
31 - - F -- OUTPUT 0 1 0 0 c5
30 - - F -- OUTPUT 0 1 0 0 c6
79 - - F -- OUTPUT 0 1 0 0 c7
98 - - B -- OUTPUT 0 1 0 0 c8
7 - - A -- OUTPUT 0 1 0 0 c9
102 - - A -- OUTPUT 0 1 0 0 c10
100 - - A -- OUTPUT 0 1 0 0 c11
12 - - C -- OUTPUT 0 1 0 0 c12
8 - - A -- OUTPUT 0 1 0 0 c13
101 - - A -- OUTPUT 0 1 0 0 c14
97 - - B -- OUTPUT 0 1 0 0 c15
92 - - C -- OUTPUT 0 1 0 0 c16
22 - - D -- OUTPUT 0 1 0 0 c17
18 - - D -- OUTPUT 0 1 0 0 c18
23 - - D -- OUTPUT 0 1 0 0 c19
19 - - D -- OUTPUT 0 1 0 0 c20
20 - - D -- OUTPUT 0 1 0 0 c21
21 - - D -- OUTPUT 0 1 0 0 c22
88 - - D -- OUTPUT 0 1 0 0 c23
144 - - A -- OUTPUT 0 1 0 0 c24
28 - - E -- OUTPUT 0 1 0 0 c25
82 - - E -- OUTPUT 0 1 0 0 c26
86 - - E -- OUTPUT 0 1 0 0 c27
29 - - E -- OUTPUT 0 1 0 0 c28
87 - - E -- OUTPUT 0 1 0 0 c29
9 - - B -- OUTPUT 0 1 0 0 c30
27 - - E -- OUTPUT 0 1 0 0 c31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\project\cpu\rom.rpt
rom
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 1 E -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_0
- - 7 F -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_1
- - 2 F -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_2
- - 4 F -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_3
- - 5 F -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_4
- - 3 F -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_5
- - 8 F -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_6
- - 6 F -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_7
- - 1 F -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_8
- - 8 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_9
- - 3 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_10
- - 2 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_11
- - 7 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_12
- - 5 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_13
- - 4 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_14
- - 6 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_15
- - 1 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_16
- - 5 D -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_17
- - 3 D -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_18
- - 2 D -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_19
- - 8 D -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_20
- - 7 D -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_21
- - 1 D -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_22
- - 6 D -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_23
- - 4 D -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_24
- - 2 E -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_25
- - 7 E -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_26
- - 8 E -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_27
- - 4 E -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_28
- - 5 E -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_29
- - 3 E -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_30
- - 6 E -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\project\cpu\rom.rpt
rom
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 3/ 96( 3%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
D: 7/ 96( 7%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
E: 7/ 96( 7%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
F: 8/ 96( 8%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project\cpu\rom.rpt
rom
** EQUATIONS **
addressin0 : INPUT;
addressin1 : INPUT;
addressin2 : INPUT;
addressin3 : INPUT;
addressin4 : INPUT;
addressin5 : INPUT;
addressin6 : INPUT;
addressin7 : INPUT;
-- Node name is 'c0'
-- Equation name is 'c0', type is output
c0 = _EC1_E;
-- Node name is 'c1'
-- Equation name is 'c1', type is output
c1 = _EC7_F;
-- Node name is 'c2'
-- Equation name is 'c2', type is output
c2 = _EC2_F;
-- Node name is 'c3'
-- Equation name is 'c3', type is output
c3 = _EC4_F;
-- Node name is 'c4'
-- Equation name is 'c4', type is output
c4 = _EC5_F;
-- Node name is 'c5'
-- Equation name is 'c5', type is output
c5 = _EC3_F;
-- Node name is 'c6'
-- Equation name is 'c6', type is output
c6 = _EC8_F;
-- Node name is 'c7'
-- Equation name is 'c7', type is output
c7 = _EC6_F;
-- Node name is 'c8'
-- Equation name is 'c8', type is output
c8 = _EC1_F;
-- Node name is 'c9'
-- Equation name is 'c9', type is output
c9 = _EC8_A;
-- Node name is 'c10'
-- Equation name is 'c10', type is output
c10 = _EC3_A;
-- Node name is 'c11'
-- Equation name is 'c11', type is output
c11 = _EC2_A;
-- Node name is 'c12'
-- Equation name is 'c12', type is output
c12 = _EC7_A;
-- Node name is 'c13'
-- Equation name is 'c13', type is output
c13 = _EC5_A;
-- Node name is 'c14'
-- Equation name is 'c14', type is output
c14 = _EC4_A;
-- Node name is 'c15'
-- Equation name is 'c15', type is output
c15 = _EC6_A;
-- Node name is 'c16'
-- Equation name is 'c16', type is output
c16 = _EC1_A;
-- Node name is 'c17'
-- Equation name is 'c17', type is output
c17 = _EC5_D;
-- Node name is 'c18'
-- Equation name is 'c18', type is output
c18 = _EC3_D;
-- Node name is 'c19'
-- Equation name is 'c19', type is output
c19 = _EC2_D;
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