mr_reg.rpt

用VHDL编的简易CPU

-- Equation name is '_LC2_B18', type is buried 
_LC2_B18 = DFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 = !EN_MBR &  _LC5_B18
         #  EN_MBR &  MBR_In9;

-- Node name is ':35' 
-- Equation name is '_LC3_B18', type is buried 
_LC3_B18 = DFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 = !EN_MBR &  _LC4_B18
         #  EN_MBR &  MBR_In8;

-- Node name is ':37' 
-- Equation name is '_LC1_A10', type is buried 
_LC1_A10 = DFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 = !EN_MBR &  _LC8_A10
         #  EN_MBR &  MBR_In7;

-- Node name is ':39' 
-- Equation name is '_LC2_A10', type is buried 
_LC2_A10 = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 = !EN_MBR &  _LC7_A10
         #  EN_MBR &  MBR_In6;

-- Node name is ':41' 
-- Equation name is '_LC6_A10', type is buried 
_LC6_A10 = DFFE( _EQ011, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 = !EN_MBR &  _LC5_A10
         #  EN_MBR &  MBR_In5;

-- Node name is ':43' 
-- Equation name is '_LC3_A10', type is buried 
_LC3_A10 = DFFE( _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 = !EN_MBR &  _LC4_A10
         #  EN_MBR &  MBR_In4;

-- Node name is ':45' 
-- Equation name is '_LC2_C12', type is buried 
_LC2_C12 = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 = !EN_MBR &  _LC8_C12
         #  EN_MBR &  MBR_In3;

-- Node name is ':47' 
-- Equation name is '_LC1_C12', type is buried 
_LC1_C12 = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 = !EN_MBR &  _LC7_C12
         #  EN_MBR &  MBR_In2;

-- Node name is ':49' 
-- Equation name is '_LC5_C12', type is buried 
_LC5_C12 = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 = !EN_MBR &  _LC4_C12
         #  EN_MBR &  MBR_In1;

-- Node name is ':51' 
-- Equation name is '_LC6_C12', type is buried 
_LC6_C12 = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 = !EN_MBR &  _LC3_C12
         #  EN_MBR &  MBR_In0;

-- Node name is ':292' 
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = LCELL( _EQ017);
  _EQ017 =  _LC1_C15 & !shiftr
         #  shiftr &  shiftr_in;

-- Node name is ':304' 
-- Equation name is '_LC7_C15', type is buried 
_LC7_C15 = LCELL( _EQ018);
  _EQ018 =  _LC3_C15 & !shiftr
         #  _LC1_C15 &  shiftr;

-- Node name is ':313' 
-- Equation name is '_LC6_C15', type is buried 
_LC6_C15 = LCELL( _EQ019);
  _EQ019 =  _LC5_C15 & !shiftr
         #  _LC3_C15 &  shiftr;

-- Node name is ':322' 
-- Equation name is '_LC4_C15', type is buried 
_LC4_C15 = LCELL( _EQ020);
  _EQ020 =  _LC2_C15 & !shiftr
         #  _LC5_C15 &  shiftr;

-- Node name is ':331' 
-- Equation name is '_LC8_B18', type is buried 
_LC8_B18 = LCELL( _EQ021);
  _EQ021 =  _LC6_B18 & !shiftr
         #  _LC2_C15 &  shiftr;

-- Node name is ':340' 
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = LCELL( _EQ022);
  _EQ022 =  _LC1_B18 & !shiftr
         #  _LC6_B18 &  shiftr;

-- Node name is ':349' 
-- Equation name is '_LC5_B18', type is buried 
_LC5_B18 = LCELL( _EQ023);
  _EQ023 =  _LC2_B18 & !shiftr
         #  _LC1_B18 &  shiftr;

-- Node name is ':358' 
-- Equation name is '_LC4_B18', type is buried 
_LC4_B18 = LCELL( _EQ024);
  _EQ024 =  _LC3_B18 & !shiftr
         #  _LC2_B18 &  shiftr;

-- Node name is ':367' 
-- Equation name is '_LC8_A10', type is buried 
_LC8_A10 = LCELL( _EQ025);
  _EQ025 =  _LC1_A10 & !shiftr
         #  _LC3_B18 &  shiftr;

-- Node name is ':376' 
-- Equation name is '_LC7_A10', type is buried 
_LC7_A10 = LCELL( _EQ026);
  _EQ026 =  _LC2_A10 & !shiftr
         #  _LC1_A10 &  shiftr;

-- Node name is ':385' 
-- Equation name is '_LC5_A10', type is buried 
_LC5_A10 = LCELL( _EQ027);
  _EQ027 =  _LC6_A10 & !shiftr
         #  _LC2_A10 &  shiftr;

-- Node name is ':394' 
-- Equation name is '_LC4_A10', type is buried 
_LC4_A10 = LCELL( _EQ028);
  _EQ028 =  _LC3_A10 & !shiftr
         #  _LC6_A10 &  shiftr;

-- Node name is ':403' 
-- Equation name is '_LC8_C12', type is buried 
_LC8_C12 = LCELL( _EQ029);
  _EQ029 =  _LC2_C12 & !shiftr
         #  _LC3_A10 &  shiftr;

-- Node name is ':412' 
-- Equation name is '_LC7_C12', type is buried 
_LC7_C12 = LCELL( _EQ030);
  _EQ030 =  _LC1_C12 & !shiftr
         #  _LC2_C12 &  shiftr;

-- Node name is ':421' 
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = LCELL( _EQ031);
  _EQ031 =  _LC5_C12 & !shiftr
         #  _LC1_C12 &  shiftr;

-- Node name is ':430' 
-- Equation name is '_LC3_C12', type is buried 
_LC3_C12 = LCELL( _EQ032);
  _EQ032 =  _LC5_C12 &  shiftr
         #  _LC6_C12 & !shiftr;



Project Information                                 d:\project1\cpu\mr_reg.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,299K