signal.fit.eqn

产生sinx＋cosx波形 用于正交调制得测试信号 一次输出正交和同相分量 verilog语言

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--E1_q_a[0] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[0] at M512_X49_Y1
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 10
--Port A Logical Depth: 32, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[0]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , E1_q_a[0]_clock_enable_0);
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_clock_enable_0 = Txen;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , E1_q_a[0]_clock_enable_0, , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out[0];

--E1_q_a[9] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[9] at M512_X49_Y1
E1_q_a[0]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , E1_q_a[0]_clock_enable_0);
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_clock_enable_0 = Txen;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , E1_q_a[0]_clock_enable_0, , , );
E1_q_a[9] = E1_q_a[0]_PORT_A_data_out[9];

--E1_q_a[8] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[8] at M512_X49_Y1
E1_q_a[0]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , E1_q_a[0]_clock_enable_0);
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_clock_enable_0 = Txen;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , E1_q_a[0]_clock_enable_0, , , );
E1_q_a[8] = E1_q_a[0]_PORT_A_data_out[8];

--E1_q_a[7] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[7] at M512_X49_Y1
E1_q_a[0]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , E1_q_a[0]_clock_enable_0);
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_clock_enable_0 = Txen;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , E1_q_a[0]_clock_enable_0, , , );
E1_q_a[7] = E1_q_a[0]_PORT_A_data_out[7];

--E1_q_a[6] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[6] at M512_X49_Y1
E1_q_a[0]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , E1_q_a[0]_clock_enable_0);
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_clock_enable_0 = Txen;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , E1_q_a[0]_clock_enable_0, , , );
E1_q_a[6] = E1_q_a[0]_PORT_A_data_out[6];

--E1_q_a[5] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[5] at M512_X49_Y1
E1_q_a[0]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , E1_q_a[0]_clock_enable_0);
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_clock_enable_0 = Txen;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , E1_q_a[0]_clock_enable_0, , , );
E1_q_a[5] = E1_q_a[0]_PORT_A_data_out[5];

--E1_q_a[4] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[4] at M512_X49_Y1
E1_q_a[0]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , E1_q_a[0]_clock_enable_0);
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_clock_enable_0 = Txen;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , E1_q_a[0]_clock_enable_0, , , );
E1_q_a[4] = E1_q_a[0]_PORT_A_data_out[4];

--E1_q_a[3] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[3] at M512_X49_Y1
E1_q_a[0]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , E1_q_a[0]_clock_enable_0);
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_clock_enable_0 = Txen;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , E1_q_a[0]_clock_enable_0, , , );
E1_q_a[3] = E1_q_a[0]_PORT_A_data_out[3];

--E1_q_a[2] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[2] at M512_X49_Y1
E1_q_a[0]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , E1_q_a[0]_clock_enable_0);
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_clock_enable_0 = Txen;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , E1_q_a[0]_clock_enable_0, , , );
E1_q_a[2] = E1_q_a[0]_PORT_A_data_out[2];

--E1_q_a[1] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[1] at M512_X49_Y1
E1_q_a[0]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , E1_q_a[0]_clock_enable_0);
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_clock_enable_0 = Txen;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , E1_q_a[0]_clock_enable_0, , , );
E1_q_a[1] = E1_q_a[0]_PORT_A_data_out[1];


--C1_addr[0] is sine:inst2|addr[0] at LC_X48_Y1_N7
--operation mode is normal

C1_addr[0]_lut_out = !C1_addr[0];
C1_addr[0] = DFFEAS(C1_addr[0]_lut_out, GLOBAL(clk), VCC, , Txen, , , , );


--C1L8 is sine:inst2|add~155 at LC_X48_Y1_N4
--operation mode is normal

C1L8 = C1_addr[0] $ C1_addr[1];


--C1L9 is sine:inst2|add~156 at LC_X48_Y1_N6
--operation mode is normal

C1_addr[2]_qfbk = C1_addr[2];
C1L9 = C1_addr[2]_qfbk $ (C1_addr[0] & C1_addr[1]);

--C1_addr[2] is sine:inst2|addr[2] at LC_X48_Y1_N6
--operation mode is normal

C1_addr[2] = DFFEAS(C1L9, GLOBAL(clk), VCC, , Txen, , , , );


--C1L10 is sine:inst2|add~157 at LC_X48_Y1_N2
--operation mode is normal

C1_addr[3]_qfbk = C1_addr[3];
C1L10 = C1_addr[3]_qfbk $ (C1_addr[0] & C1_addr[1] & C1_addr[2]);

--C1_addr[3] is sine:inst2|addr[3] at LC_X48_Y1_N2
--operation mode is normal

C1_addr[3] = DFFEAS(C1L10, GLOBAL(clk), VCC, , Txen, , , , );


--C1L11 is sine:inst2|add~158 at LC_X48_Y1_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_addr[1]_qfbk = C1_addr[1];
C1L11 = C1_addr[0] & (C1_addr[1]_qfbk);

--C1_addr[1] is sine:inst2|addr[1] at LC_X48_Y1_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_addr[1] = DFFEAS(C1L11, GLOBAL(clk), VCC, , Txen, C1L8, , , VCC);


--C1L12 is sine:inst2|add~159 at LC_X48_Y1_N8
--operation mode is normal

C1_addr[4]_qfbk = C1_addr[4];
C1L12 = C1_addr[4]_qfbk $ (C1_addr[3] & C1L11 & C1_addr[2]);

--C1_addr[4] is sine:inst2|addr[4] at LC_X48_Y1_N8
--operation mode is normal

C1_addr[4] = DFFEAS(C1L12, GLOBAL(clk), VCC, , Txen, , , , );


--rst1 is rst1 at PIN_K16
--operation mode is input

rst1 = INPUT();


--clk is clk at PIN_L2
--operation mode is input

clk = INPUT();


--Txen is Txen at PIN_W5
--operation mode is input

Txen = INPUT();


--data[11] is data[11] at PIN_N7
--operation mode is output

data[11] = OUTPUT(E1_q_a[0]);


--data[10] is data[10] at PIN_T5
--operation mode is output

data[10] = OUTPUT(E1_q_a[1]);


--data[9] is data[9] at PIN_V3
--operation mode is output

data[9] = OUTPUT(E1_q_a[2]);


--data[8] is data[8] at PIN_W1
--operation mode is output

data[8] = OUTPUT(E1_q_a[3]);


--data[7] is data[7] at PIN_V4
--operation mode is output

data[7] = OUTPUT(E1_q_a[4]);


--data[6] is data[6] at PIN_AB6
--operation mode is output

data[6] = OUTPUT(E1_q_a[5]);


--data[5] is data[5] at PIN_W2
--operation mode is output

data[5] = OUTPUT(E1_q_a[1]);


--data[4] is data[4] at PIN_P7
--operation mode is output

data[4] = OUTPUT(E1_q_a[6]);


--data[3] is data[3] at PIN_AA5
--operation mode is output

data[3] = OUTPUT(E1_q_a[7]);


--data[2] is data[2] at PIN_A5
--operation mode is output

data[2] = OUTPUT(E1_q_a[8]);


--data[1] is data[1] at PIN_Y2
--operation mode is output

data[1] = OUTPUT(E1_q_a[9]);


--data[0] is data[0] at PIN_Y4
--operation mode is output

data[0] = OUTPUT(E1_q_a[9]);


--C1L3 is sine:inst2|addr[0]~20 at LC_X48_Y1_N9
--operation mode is normal

C1L3 = !C1_addr[0];