signal.fit.qmsg

产生sinx＋cosx波形 用于正交调制得测试信号 一次输出正交和同相分量 verilog语言

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.872 ns register memory " "Info: Estimated most critical path is register to memory delay of 1.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sine:inst2\|addr\[0\] 1 REG LAB_X48_Y1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X48_Y1; Fanout = 8; REG Node = 'sine:inst2\|addr\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "" { sine:inst2|addr[0] } "NODE_NAME" } "" } } { "sine.v" "" { Text "D:/altera/quartus51/signal/sine.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.193 ns) + CELL(0.366 ns) 0.559 ns sine:inst2\|add~158 2 COMB LAB_X48_Y1 2 " "Info: 2: + IC(0.193 ns) + CELL(0.366 ns) = 0.559 ns; Loc. = LAB_X48_Y1; Fanout = 2; COMB Node = 'sine:inst2\|add~158'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "0.559 ns" { sine:inst2|addr[0] sine:inst2|add~158 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.366 ns) 1.061 ns sine:inst2\|add~159 3 COMB LAB_X48_Y1 10 " "Info: 3: + IC(0.136 ns) + CELL(0.366 ns) = 1.061 ns; Loc. = LAB_X48_Y1; Fanout = 10; COMB Node = 'sine:inst2\|add~159'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "0.502 ns" { sine:inst2|add~158 sine:inst2|add~159 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.231 ns) 1.872 ns ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg4 4 MEM M512_X49_Y1 1 " "Info: 4: + IC(0.580 ns) + CELL(0.231 ns) = 1.872 ns; Loc. = M512_X49_Y1; Fanout = 1; MEM Node = 'ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "0.811 ns" { sine:inst2|add~159 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "db/altsyncram_d1m.tdf" "" { Text "D:/altera/quartus51/signal/db/altsyncram_d1m.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.963 ns ( 51.44 % ) " "Info: Total cell delay = 0.963 ns ( 51.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.909 ns ( 48.56 % ) " "Info: Total interconnect delay = 0.909 ns ( 48.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "1.872 ns" { sine:inst2|addr[0] sine:inst2|add~158 sine:inst2|add~159 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 10 15:37:40 2008 " "Info: Processing ended: Thu Apr 10 15:37:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}