signal.tan.qmsg

产生sinx＋cosx波形 用于正交调制得测试信号 一次输出正交和同相分量 verilog语言

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sine:inst2\|addr\[0\] memory ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg4 366.84 MHz 2.726 ns Internal " "Info: Clock \"clk\" has Internal fmax of 366.84 MHz between source register \"sine:inst2\|addr\[0\]\" and destination memory \"ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg4\" (period= 2.726 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.230 ns + Longest register memory " "Info: + Longest register to memory delay is 2.230 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sine:inst2\|addr\[0\] 1 REG LC_X48_Y1_N7 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X48_Y1_N7; Fanout = 8; REG Node = 'sine:inst2\|addr\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "" { sine:inst2|addr[0] } "NODE_NAME" } "" } } { "sine.v" "" { Text "D:/altera/quartus51/signal/sine.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.366 ns) 0.810 ns sine:inst2\|add~158 2 COMB LC_X48_Y1_N5 2 " "Info: 2: + IC(0.444 ns) + CELL(0.366 ns) = 0.810 ns; Loc. = LC_X48_Y1_N5; Fanout = 2; COMB Node = 'sine:inst2\|add~158'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "0.810 ns" { sine:inst2|addr[0] sine:inst2|add~158 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.280 ns) 1.392 ns sine:inst2\|add~159 3 COMB LC_X48_Y1_N8 1 " "Info: 3: + IC(0.302 ns) + CELL(0.280 ns) = 1.392 ns; Loc. = LC_X48_Y1_N8; Fanout = 1; COMB Node = 'sine:inst2\|add~159'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "0.582 ns" { sine:inst2|add~158 sine:inst2|add~159 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.607 ns) + CELL(0.231 ns) 2.230 ns ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg4 4 MEM M512_X49_Y1 10 " "Info: 4: + IC(0.607 ns) + CELL(0.231 ns) = 2.230 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "0.838 ns" { sine:inst2|add~159 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "db/altsyncram_d1m.tdf" "" { Text "D:/altera/quartus51/signal/db/altsyncram_d1m.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.877 ns ( 39.33 % ) " "Info: Total cell delay = 0.877 ns ( 39.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.353 ns ( 60.67 % ) " "Info: Total interconnect delay = 1.353 ns ( 60.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.230 ns" { sine:inst2|addr[0] sine:inst2|add~158 sine:inst2|add~159 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.230 ns" { sine:inst2|addr[0] sine:inst2|add~158 sine:inst2|add~159 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.444ns 0.302ns 0.607ns } { 0.000ns 0.366ns 0.280ns 0.231ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.230 ns - Smallest " "Info: - Smallest clock skew is -0.230 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.687 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.687 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "" { clk } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "D:/altera/quartus51/signal/signal.bdf" { { 96 24 192 112 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.650 ns) + CELL(0.312 ns) 2.687 ns ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg4 2 MEM M512_X49_Y1 10 " "Info: 2: + IC(1.650 ns) + CELL(0.312 ns) = 2.687 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "1.962 ns" { clk ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "db/altsyncram_d1m.tdf" "" { Text "D:/altera/quartus51/signal/db/altsyncram_d1m.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.037 ns ( 38.59 % ) " "Info: Total cell delay = 1.037 ns ( 38.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.650 ns ( 61.41 % ) " "Info: Total interconnect delay = 1.650 ns ( 61.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.687 ns" { clk ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~out0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.312ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.917 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "" { clk } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "D:/altera/quartus51/signal/signal.bdf" { { 96 24 192 112 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.650 ns) + CELL(0.542 ns) 2.917 ns sine:inst2\|addr\[0\] 2 REG LC_X48_Y1_N7 8 " "Info: 2: + IC(1.650 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X48_Y1_N7; Fanout = 8; REG Node = 'sine:inst2\|addr\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.192 ns" { clk sine:inst2|addr[0] } "NODE_NAME" } "" } } { "sine.v" "" { Text "D:/altera/quartus51/signal/sine.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.44 % ) " "Info: Total cell delay = 1.267 ns ( 43.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.650 ns ( 56.56 % ) " "Info: Total interconnect delay = 1.650 ns ( 56.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.917 ns" { clk sine:inst2|addr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 sine:inst2|addr[0] } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.687 ns" { clk ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~out0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.312ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.917 ns" { clk sine:inst2|addr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 sine:inst2|addr[0] } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "sine.v" "" { Text "D:/altera/quartus51/signal/sine.v" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.110 ns + " "Info: + Micro setup delay of destination is 0.110 ns" {  } { { "db/altsyncram_d1m.tdf" "" { Text "D:/altera/quartus51/signal/db/altsyncram_d1m.tdf" 44 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.230 ns" { sine:inst2|addr[0] sine:inst2|add~158 sine:inst2|add~159 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.230 ns" { sine:inst2|addr[0] sine:inst2|add~158 sine:inst2|add~159 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.444ns 0.302ns 0.607ns } { 0.000ns 0.366ns 0.280ns 0.231ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.687 ns" { clk ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~out0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.312ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.917 ns" { clk sine:inst2|addr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 sine:inst2|addr[0] } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0 Txen clk 2.691 ns memory " "Info: tsu for memory \"ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0\" (data pin = \"Txen\", clock pin = \"clk\") is 2.691 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.268 ns + Longest pin memory " "Info: + Longest pin to memory delay is 5.268 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns Txen 1 PIN PIN_W5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W5; Fanout = 10; PIN Node = 'Txen'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "" { Txen } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "D:/altera/quartus51/signal/signal.bdf" { { 112 24 192 128 "Txen" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.765 ns) + CELL(0.416 ns) 5.268 ns ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M512_X49_Y1 10 " "Info: 2: + IC(3.765 ns) + CELL(0.416 ns) = 5.268 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "4.181 ns" { Txen ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_d1m.tdf" "" { Text "D:/altera/quartus51/signal/db/altsyncram_d1m.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.503 ns ( 28.53 % ) " "Info: Total cell delay = 1.503 ns ( 28.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.765 ns ( 71.47 % ) " "Info: Total interconnect delay = 3.765 ns ( 71.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "5.268 ns" { Txen ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.268 ns" { Txen Txen~out0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 3.765ns } { 0.000ns 1.087ns 0.416ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.110 ns + " "Info: + Micro setup delay of destination is 0.110 ns" {  } { { "db/altsyncram_d1m.tdf" "" { Text "D:/altera/quartus51/signal/db/altsyncram_d1m.tdf" 44 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.687 ns - Shortest memory " "Info: - Shortest clock path from clock \"clk\" to destination memory is 2.687 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "" { clk } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "D:/altera/quartus51/signal/signal.bdf" { { 96 24 192 112 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.650 ns) + CELL(0.312 ns) 2.687 ns ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M512_X49_Y1 10 " "Info: 2: + IC(1.650 ns) + CELL(0.312 ns) = 2.687 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "1.962 ns" { clk ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_d1m.tdf" "" { Text "D:/altera/quartus51/signal/db/altsyncram_d1m.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.037 ns ( 38.59 % ) " "Info: Total cell delay = 1.037 ns ( 38.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.650 ns ( 61.41 % ) " "Info: Total interconnect delay = 1.650 ns ( 61.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.687 ns" { clk ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~out0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.312ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "5.268 ns" { Txen ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.268 ns" { Txen Txen~out0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 3.765ns } { 0.000ns 1.087ns 0.416ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.687 ns" { clk ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~out0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.312ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[2\] ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0 10.072 ns memory " "Info: tco from clock \"clk\" to destination pin \"data\[2\]\" through memory \"ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0\" is 10.072 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.687 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.687 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "" { clk } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "D:/altera/quartus51/signal/signal.bdf" { { 96 24 192 112 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.650 ns) + CELL(0.312 ns) 2.687 ns ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M512_X49_Y1 10 " "Info: 2: + IC(1.650 ns) + CELL(0.312 ns) = 2.687 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "1.962 ns" { clk ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_d1m.tdf" "" { Text "D:/altera/quartus51/signal/db/altsyncram_d1m.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.037 ns ( 38.59 % ) " "Info: Total cell delay = 1.037 ns ( 38.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.650 ns ( 61.41 % ) " "Info: Total interconnect delay = 1.650 ns ( 61.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.687 ns" { clk ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~out0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.312ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.519 ns + " "Info: + Micro clock to output delay of source is 0.519 ns" {  } { { "db/altsyncram_d1m.tdf" "" { Text "D:/altera/quartus51/signal/db/altsyncram_d1m.tdf" 44 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.866 ns + Longest memory pin " "Info: + Longest memory to pin delay is 6.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M512_X49_Y1 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "" { ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_d1m.tdf" "" { Text "D:/altera/quartus51/signal/db/altsyncram_d1m.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.613 ns) 2.613 ns ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|q_a\[8\] 2 MEM M512_X49_Y1 1 " "Info: 2: + IC(0.000 ns) + CELL(2.613 ns) = 2.613 ns; Loc. = M512_X49_Y1; Fanout = 1; MEM Node = 'ram:inst\|altsyncram:data_rtl_0\|altsyncram_d1m:auto_generated\|q_a\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.613 ns" { ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[8] } "NODE_NAME" } "" } } { "db/altsyncram_d1m.tdf" "" { Text "D:/altera/quartus51/signal/db/altsyncram_d1m.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.849 ns) + CELL(2.404 ns) 6.866 ns data\[2\] 3 PIN PIN_A5 0 " "Info: 3: + IC(1.849 ns) + CELL(2.404 ns) = 6.866 ns; Loc. = PIN_A5; Fanout = 0; PIN Node = 'data\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "4.253 ns" { ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[8] data[2] } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "D:/altera/quartus51/signal/signal.bdf" { { 96 632 808 112 "data\[11..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.017 ns ( 73.07 % ) " "Info: Total cell delay = 5.017 ns ( 73.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.849 ns ( 26.93 % ) " "Info: Total interconnect delay = 1.849 ns ( 26.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "6.866 ns" { ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[8] data[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.866 ns" { ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[8] data[2] } { 0.000ns 0.000ns 1.849ns } { 0.000ns 2.613ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.687 ns" { clk ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~out0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.312ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "6.866 ns" { ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[8] data[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.866 ns" { ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[8] data[2] } { 0.000ns 0.000ns 1.849ns } { 0.000ns 2.613ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "sine:inst2\|addr\[0\] Txen clk -2.484 ns register " "Info: th for register \"sine:inst2\|addr\[0\]\" (data pin = \"Txen\", clock pin = \"clk\") is -2.484 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.917 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "" { clk } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "D:/altera/quartus51/signal/signal.bdf" { { 96 24 192 112 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.650 ns) + CELL(0.542 ns) 2.917 ns sine:inst2\|addr\[0\] 2 REG LC_X48_Y1_N7 8 " "Info: 2: + IC(1.650 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X48_Y1_N7; Fanout = 8; REG Node = 'sine:inst2\|addr\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.192 ns" { clk sine:inst2|addr[0] } "NODE_NAME" } "" } } { "sine.v" "" { Text "D:/altera/quartus51/signal/sine.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.44 % ) " "Info: Total cell delay = 1.267 ns ( 43.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.650 ns ( 56.56 % ) " "Info: Total interconnect delay = 1.650 ns ( 56.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.917 ns" { clk sine:inst2|addr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 sine:inst2|addr[0] } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "sine.v" "" { Text "D:/altera/quartus51/signal/sine.v" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.501 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns Txen 1 PIN PIN_W5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W5; Fanout = 10; PIN Node = 'Txen'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "" { Txen } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "D:/altera/quartus51/signal/signal.bdf" { { 112 24 192 128 "Txen" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.709 ns) + CELL(0.705 ns) 5.501 ns sine:inst2\|addr\[0\] 2 REG LC_X48_Y1_N7 8 " "Info: 2: + IC(3.709 ns) + CELL(0.705 ns) = 5.501 ns; Loc. = LC_X48_Y1_N7; Fanout = 8; REG Node = 'sine:inst2\|addr\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "4.414 ns" { Txen sine:inst2|addr[0] } "NODE_NAME" } "" } } { "sine.v" "" { Text "D:/altera/quartus51/signal/sine.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.792 ns ( 32.58 % ) " "Info: Total cell delay = 1.792 ns ( 32.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.709 ns ( 67.42 % ) " "Info: Total interconnect delay = 3.709 ns ( 67.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "5.501 ns" { Txen sine:inst2|addr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.501 ns" { Txen Txen~out0 sine:inst2|addr[0] } { 0.000ns 0.000ns 3.709ns } { 0.000ns 1.087ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "2.917 ns" { clk sine:inst2|addr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 sine:inst2|addr[0] } { 0.000ns 0.000ns 1.650ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "signal" "UNKNOWN" "V1" "D:/altera/quartus51/signal/db/signal.quartus_db" { Floorplan "D:/altera/quartus51/signal/" "" "5.501 ns" { Txen sine:inst2|addr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.501 ns" { Txen Txen~out0 sine:inst2|addr[0] } { 0.000ns 0.000ns 3.709ns } { 0.000ns 1.087ns 0.705ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}