signal.map.eqn

产生sinx＋cosx波形 用于正交调制得测试信号 一次输出正交和同相分量 verilog语言

-- Copyright (C) 1991-2005 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--E1_q_a[0] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[0]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , E1_q_a[0]_clock_enable_0);
E1_q_a[0]_clock_0 = clk;
E1_q_a[0]_clock_enable_0 = Txen;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , E1_q_a[0]_clock_enable_0, , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out[0];


--E1_q_a[1] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[1]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , E1_q_a[1]_clock_enable_0);
E1_q_a[1]_clock_0 = clk;
E1_q_a[1]_clock_enable_0 = Txen;
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , E1_q_a[1]_clock_enable_0, , , );
E1_q_a[1] = E1_q_a[1]_PORT_A_data_out[0];


--E1_q_a[2] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[2]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[2]_PORT_A_address_reg = DFFE(E1_q_a[2]_PORT_A_address, E1_q_a[2]_clock_0, , , E1_q_a[2]_clock_enable_0);
E1_q_a[2]_clock_0 = clk;
E1_q_a[2]_clock_enable_0 = Txen;
E1_q_a[2]_PORT_A_data_out = MEMORY(, , E1_q_a[2]_PORT_A_address_reg, , , , , , E1_q_a[2]_clock_0, , E1_q_a[2]_clock_enable_0, , , );
E1_q_a[2] = E1_q_a[2]_PORT_A_data_out[0];


--E1_q_a[3] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[3]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[3]_PORT_A_address_reg = DFFE(E1_q_a[3]_PORT_A_address, E1_q_a[3]_clock_0, , , E1_q_a[3]_clock_enable_0);
E1_q_a[3]_clock_0 = clk;
E1_q_a[3]_clock_enable_0 = Txen;
E1_q_a[3]_PORT_A_data_out = MEMORY(, , E1_q_a[3]_PORT_A_address_reg, , , , , , E1_q_a[3]_clock_0, , E1_q_a[3]_clock_enable_0, , , );
E1_q_a[3] = E1_q_a[3]_PORT_A_data_out[0];


--E1_q_a[4] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[4]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[4]_PORT_A_address_reg = DFFE(E1_q_a[4]_PORT_A_address, E1_q_a[4]_clock_0, , , E1_q_a[4]_clock_enable_0);
E1_q_a[4]_clock_0 = clk;
E1_q_a[4]_clock_enable_0 = Txen;
E1_q_a[4]_PORT_A_data_out = MEMORY(, , E1_q_a[4]_PORT_A_address_reg, , , , , , E1_q_a[4]_clock_0, , E1_q_a[4]_clock_enable_0, , , );
E1_q_a[4] = E1_q_a[4]_PORT_A_data_out[0];


--E1_q_a[5] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[5]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[5]_PORT_A_address_reg = DFFE(E1_q_a[5]_PORT_A_address, E1_q_a[5]_clock_0, , , E1_q_a[5]_clock_enable_0);
E1_q_a[5]_clock_0 = clk;
E1_q_a[5]_clock_enable_0 = Txen;
E1_q_a[5]_PORT_A_data_out = MEMORY(, , E1_q_a[5]_PORT_A_address_reg, , , , , , E1_q_a[5]_clock_0, , E1_q_a[5]_clock_enable_0, , , );
E1_q_a[5] = E1_q_a[5]_PORT_A_data_out[0];


--E1_q_a[6] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[6]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[6]_PORT_A_address_reg = DFFE(E1_q_a[6]_PORT_A_address, E1_q_a[6]_clock_0, , , E1_q_a[6]_clock_enable_0);
E1_q_a[6]_clock_0 = clk;
E1_q_a[6]_clock_enable_0 = Txen;
E1_q_a[6]_PORT_A_data_out = MEMORY(, , E1_q_a[6]_PORT_A_address_reg, , , , , , E1_q_a[6]_clock_0, , E1_q_a[6]_clock_enable_0, , , );
E1_q_a[6] = E1_q_a[6]_PORT_A_data_out[0];


--E1_q_a[7] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[7]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , E1_q_a[7]_clock_enable_0);
E1_q_a[7]_clock_0 = clk;
E1_q_a[7]_clock_enable_0 = Txen;
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , E1_q_a[7]_clock_enable_0, , , );
E1_q_a[7] = E1_q_a[7]_PORT_A_data_out[0];


--E1_q_a[8] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[8]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[8]_PORT_A_address_reg = DFFE(E1_q_a[8]_PORT_A_address, E1_q_a[8]_clock_0, , , E1_q_a[8]_clock_enable_0);
E1_q_a[8]_clock_0 = clk;
E1_q_a[8]_clock_enable_0 = Txen;
E1_q_a[8]_PORT_A_data_out = MEMORY(, , E1_q_a[8]_PORT_A_address_reg, , , , , , E1_q_a[8]_clock_0, , E1_q_a[8]_clock_enable_0, , , );
E1_q_a[8] = E1_q_a[8]_PORT_A_data_out[0];


--E1_q_a[9] is ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[9]_PORT_A_address = BUS(C1L3, C1L8, C1L9, C1L10, C1L12);
E1_q_a[9]_PORT_A_address_reg = DFFE(E1_q_a[9]_PORT_A_address, E1_q_a[9]_clock_0, , , E1_q_a[9]_clock_enable_0);
E1_q_a[9]_clock_0 = clk;
E1_q_a[9]_clock_enable_0 = Txen;
E1_q_a[9]_PORT_A_data_out = MEMORY(, , E1_q_a[9]_PORT_A_address_reg, , , , , , E1_q_a[9]_clock_0, , E1_q_a[9]_clock_enable_0, , , );
E1_q_a[9] = E1_q_a[9]_PORT_A_data_out[0];


--C1_addr[0] is sine:inst2|addr[0]
--operation mode is normal

C1_addr[0]_lut_out = !C1_addr[0];
C1_addr[0] = DFFEAS(C1_addr[0]_lut_out, clk, VCC, , Txen, , , , );


--C1_addr[1] is sine:inst2|addr[1]
--operation mode is normal

C1_addr[1]_lut_out = C1L8;
C1_addr[1] = DFFEAS(C1_addr[1]_lut_out, clk, VCC, , Txen, , , , );


--C1L8 is sine:inst2|add~155
--operation mode is normal

C1L8 = C1_addr[0] $ C1_addr[1];


--C1_addr[2] is sine:inst2|addr[2]
--operation mode is normal

C1_addr[2]_lut_out = C1L9;
C1_addr[2] = DFFEAS(C1_addr[2]_lut_out, clk, VCC, , Txen, , , , );


--C1L9 is sine:inst2|add~156
--operation mode is normal

C1L9 = C1_addr[2] $ (C1_addr[0] & C1_addr[1]);


--C1_addr[3] is sine:inst2|addr[3]
--operation mode is normal

C1_addr[3]_lut_out = C1L10;
C1_addr[3] = DFFEAS(C1_addr[3]_lut_out, clk, VCC, , Txen, , , , );


--C1L10 is sine:inst2|add~157
--operation mode is normal

C1L10 = C1_addr[3] $ (C1_addr[0] & C1_addr[1] & C1_addr[2]);


--C1_addr[4] is sine:inst2|addr[4]
--operation mode is normal

C1_addr[4]_lut_out = C1L12;
C1_addr[4] = DFFEAS(C1_addr[4]_lut_out, clk, VCC, , Txen, , , , );


--C1L11 is sine:inst2|add~158
--operation mode is normal

C1L11 = C1_addr[0] & C1_addr[1];


--C1L12 is sine:inst2|add~159
--operation mode is normal

C1L12 = C1_addr[4] $ (C1_addr[2] & C1L11 & C1_addr[3]);


--rst1 is rst1
--operation mode is input

rst1 = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--Txen is Txen
--operation mode is input

Txen = INPUT();


--data[11] is data[11]
--operation mode is output

data[11] = OUTPUT(E1_q_a[0]);


--data[10] is data[10]
--operation mode is output

data[10] = OUTPUT(E1_q_a[1]);


--data[9] is data[9]
--operation mode is output

data[9] = OUTPUT(E1_q_a[2]);


--data[8] is data[8]
--operation mode is output

data[8] = OUTPUT(E1_q_a[3]);


--data[7] is data[7]
--operation mode is output

data[7] = OUTPUT(E1_q_a[4]);


--data[6] is data[6]
--operation mode is output

data[6] = OUTPUT(E1_q_a[5]);


--data[5] is data[5]
--operation mode is output

data[5] = OUTPUT(E1_q_a[1]);


--data[4] is data[4]
--operation mode is output

data[4] = OUTPUT(E1_q_a[6]);


--data[3] is data[3]
--operation mode is output

data[3] = OUTPUT(E1_q_a[7]);


--data[2] is data[2]
--operation mode is output

data[2] = OUTPUT(E1_q_a[8]);


--data[1] is data[1]
--operation mode is output

data[1] = OUTPUT(E1_q_a[9]);


--data[0] is data[0]
--operation mode is output

data[0] = OUTPUT(E1_q_a[9]);


--C1L3 is sine:inst2|addr[0]~20
--operation mode is normal

C1L3 = !C1_addr[0];