signal.tan.rpt

产生sinx＋cosx波形 用于正交调制得测试信号 一次输出正交和同相分量 verilog语言

; N/A   ; None         ; 9.098 ns   ; ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 ; data[9]  ; clk        ;
; N/A   ; None         ; 9.098 ns   ; ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg1 ; data[9]  ; clk        ;
; N/A   ; None         ; 9.098 ns   ; ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg2 ; data[9]  ; clk        ;
; N/A   ; None         ; 9.098 ns   ; ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg3 ; data[9]  ; clk        ;
; N/A   ; None         ; 9.098 ns   ; ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 ; data[9]  ; clk        ;
+-------+--------------+------------+----------------------------------------------------------------------------------------------+----------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                       ;
+---------------+-------------+-----------+------+----------------------------------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                                                                                           ; To Clock ;
+---------------+-------------+-----------+------+----------------------------------------------------------------------------------------------+----------+
; N/A           ; None        ; -2.484 ns ; Txen ; sine:inst2|addr[0]                                                                           ; clk      ;
; N/A           ; None        ; -2.484 ns ; Txen ; sine:inst2|addr[1]                                                                           ; clk      ;
; N/A           ; None        ; -2.484 ns ; Txen ; sine:inst2|addr[2]                                                                           ; clk      ;
; N/A           ; None        ; -2.484 ns ; Txen ; sine:inst2|addr[3]                                                                           ; clk      ;
; N/A           ; None        ; -2.484 ns ; Txen ; sine:inst2|addr[4]                                                                           ; clk      ;
; N/A           ; None        ; -2.547 ns ; Txen ; ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0 ; clk      ;
; N/A           ; None        ; -2.547 ns ; Txen ; ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg1 ; clk      ;
; N/A           ; None        ; -2.547 ns ; Txen ; ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg2 ; clk      ;
; N/A           ; None        ; -2.547 ns ; Txen ; ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg3 ; clk      ;
; N/A           ; None        ; -2.547 ns ; Txen ; ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4 ; clk      ;
+---------------+-------------+-----------+------+----------------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 10 15:37:53 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off signal -c signal --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 366.84 MHz between source register "sine:inst2|addr[0]" and destination memory "ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4" (period= 2.726 ns)
    Info: + Longest register to memory delay is 2.230 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X48_Y1_N7; Fanout = 8; REG Node = 'sine:inst2|addr[0]'
        Info: 2: + IC(0.444 ns) + CELL(0.366 ns) = 0.810 ns; Loc. = LC_X48_Y1_N5; Fanout = 2; COMB Node = 'sine:inst2|add~158'
        Info: 3: + IC(0.302 ns) + CELL(0.280 ns) = 1.392 ns; Loc. = LC_X48_Y1_N8; Fanout = 1; COMB Node = 'sine:inst2|add~159'
        Info: 4: + IC(0.607 ns) + CELL(0.231 ns) = 2.230 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4'
        Info: Total cell delay = 0.877 ns ( 39.33 % )
        Info: Total interconnect delay = 1.353 ns ( 60.67 % )
    Info: - Smallest clock skew is -0.230 ns
        Info: + Shortest clock path from clock "clk" to destination memory is 2.687 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'
            Info: 2: + IC(1.650 ns) + CELL(0.312 ns) = 2.687 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4'
            Info: Total cell delay = 1.037 ns ( 38.59 % )
            Info: Total interconnect delay = 1.650 ns ( 61.41 % )
        Info: - Longest clock path from clock "clk" to source register is 2.917 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'
            Info: 2: + IC(1.650 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X48_Y1_N7; Fanout = 8; REG Node = 'sine:inst2|addr[0]'
            Info: Total cell delay = 1.267 ns ( 43.44 % )
            Info: Total interconnect delay = 1.650 ns ( 56.56 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.110 ns
Info: tsu for memory "ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0" (data pin = "Txen", clock pin = "clk") is 2.691 ns
    Info: + Longest pin to memory delay is 5.268 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W5; Fanout = 10; PIN Node = 'Txen'
        Info: 2: + IC(3.765 ns) + CELL(0.416 ns) = 5.268 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0'
        Info: Total cell delay = 1.503 ns ( 28.53 % )
        Info: Total interconnect delay = 3.765 ns ( 71.47 % )
    Info: + Micro setup delay of destination is 0.110 ns
    Info: - Shortest clock path from clock "clk" to destination memory is 2.687 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(1.650 ns) + CELL(0.312 ns) = 2.687 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0'
        Info: Total cell delay = 1.037 ns ( 38.59 % )
        Info: Total interconnect delay = 1.650 ns ( 61.41 % )
Info: tco from clock "clk" to destination pin "data[2]" through memory "ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0" is 10.072 ns
    Info: + Longest clock path from clock "clk" to source memory is 2.687 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(1.650 ns) + CELL(0.312 ns) = 2.687 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0'
        Info: Total cell delay = 1.037 ns ( 38.59 % )
        Info: Total interconnect delay = 1.650 ns ( 61.41 % )
    Info: + Micro clock to output delay of source is 0.519 ns
    Info: + Longest memory to pin delay is 6.866 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X49_Y1; Fanout = 10; MEM Node = 'ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg0'
        Info: 2: + IC(0.000 ns) + CELL(2.613 ns) = 2.613 ns; Loc. = M512_X49_Y1; Fanout = 1; MEM Node = 'ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|q_a[8]'
        Info: 3: + IC(1.849 ns) + CELL(2.404 ns) = 6.866 ns; Loc. = PIN_A5; Fanout = 0; PIN Node = 'data[2]'
        Info: Total cell delay = 5.017 ns ( 73.07 % )
        Info: Total interconnect delay = 1.849 ns ( 26.93 % )
Info: th for register "sine:inst2|addr[0]" (data pin = "Txen", clock pin = "clk") is -2.484 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.917 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(1.650 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X48_Y1_N7; Fanout = 8; REG Node = 'sine:inst2|addr[0]'
        Info: Total cell delay = 1.267 ns ( 43.44 % )
        Info: Total interconnect delay = 1.650 ns ( 56.56 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.501 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W5; Fanout = 10; PIN Node = 'Txen'
        Info: 2: + IC(3.709 ns) + CELL(0.705 ns) = 5.501 ns; Loc. = LC_X48_Y1_N7; Fanout = 8; REG Node = 'sine:inst2|addr[0]'
        Info: Total cell delay = 1.792 ns ( 32.58 % )
        Info: Total interconnect delay = 3.709 ns ( 67.42 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Apr 10 15:37:54 2008
    Info: Elapsed time: 00:00:02