signal.tan.summary

产生sinx＋cosx波形 用于正交调制得测试信号 一次输出正交和同相分量 verilog语言

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.691 ns
From           : Txen
To             : ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.072 ns
From           : ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4
To             : data[2]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.484 ns
From           : Txen
To             : sine:inst2|addr[4]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 366.84 MHz ( period = 2.726 ns )
From           : sine:inst2|addr[0]
To             : ram:inst|altsyncram:data_rtl_0|altsyncram_d1m:auto_generated|ram_block1a0~porta_address_reg4
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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