dled.tan.qmsg

来自「很多vhdl例程代码」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off dled -c dled --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dled -c dled --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "int_div:inst\|ClockOut register scan_led:inst1\|disp_dat\[0\] register scan_led:inst1\|count\[2\] 16.851 ns " "Info: Slack time is 16.851 ns for clock \"int_div:inst\|ClockOut\" between source register \"scan_led:inst1\|disp_dat\[0\]\" and destination register \"scan_led:inst1\|count\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination int_div:inst\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"int_div:inst\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source int_div:inst\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"int_div:inst\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst\|ClockOut destination 5.021 ns + Shortest register " "Info: + Shortest clock path from clock \"int_div:inst\|ClockOut\" to destination register is 5.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|ClockOut 1 CLK LC_X11_Y12_N5 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y12_N5; Fanout = 13; CLK Node = 'int_div:inst\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { int_div:inst|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.310 ns) + CELL(0.711 ns) 5.021 ns scan_led:inst1\|count\[2\] 2 REG LC_X27_Y12_N3 10 " "Info: 2: + IC(4.310 ns) + CELL(0.711 ns) = 5.021 ns; Loc. = LC_X27_Y12_N3; Fanout = 10; REG Node = 'scan_led:inst1\|count\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.16 % " "Info: Total cell delay = 0.711 ns ( 14.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.310 ns 85.84 % " "Info: Total interconnect delay = 4.310 ns ( 85.84 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.000ns 4.310ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst\|ClockOut source 5.021 ns - Longest register " "Info: - Longest clock path from clock \"int_div:inst\|ClockOut\" to source register is 5.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|ClockOut 1 CLK LC_X11_Y12_N5 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y12_N5; Fanout = 13; CLK Node = 'int_div:inst\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { int_div:inst|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.310 ns) + CELL(0.711 ns) 5.021 ns scan_led:inst1\|disp_dat\[0\] 2 REG LC_X26_Y12_N3 20 " "Info: 2: + IC(4.310 ns) + CELL(0.711 ns) = 5.021 ns; Loc. = LC_X26_Y12_N3; Fanout = 20; REG Node = 'scan_led:inst1\|disp_dat\[0\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|disp_dat[0] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.16 % " "Info: Total cell delay = 0.711 ns ( 14.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.310 ns 85.84 % " "Info: Total interconnect delay = 4.310 ns ( 85.84 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|disp_dat[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|disp_dat[0] } { 0.000ns 4.310ns } { 0.000ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.000ns 4.310ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|disp_dat[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|disp_dat[0] } { 0.000ns 4.310ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 40 -1 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.000ns 4.310ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|disp_dat[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|disp_dat[0] } { 0.000ns 4.310ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.888 ns - Longest register register " "Info: - Longest register to register delay is 2.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan_led:inst1\|disp_dat\[0\] 1 REG LC_X26_Y12_N3 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y12_N3; Fanout = 20; REG Node = 'scan_led:inst1\|disp_dat\[0\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { scan_led:inst1|disp_dat[0] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.966 ns) + CELL(0.590 ns) 1.556 ns scan_led:inst1\|Mux~261 2 COMB LC_X27_Y12_N7 1 " "Info: 2: + IC(0.966 ns) + CELL(0.590 ns) = 1.556 ns; Loc. = LC_X27_Y12_N7; Fanout = 1; COMB Node = 'scan_led:inst1\|Mux~261'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "1.556 ns" { scan_led:inst1|disp_dat[0] scan_led:inst1|Mux~261 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.867 ns) 2.888 ns scan_led:inst1\|count\[2\] 3 REG LC_X27_Y12_N3 10 " "Info: 3: + IC(0.465 ns) + CELL(0.867 ns) = 2.888 ns; Loc. = LC_X27_Y12_N3; Fanout = 10; REG Node = 'scan_led:inst1\|count\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "1.332 ns" { scan_led:inst1|Mux~261 scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns 50.45 % " "Info: Total cell delay = 1.457 ns ( 50.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.431 ns 49.55 % " "Info: Total interconnect delay = 1.431 ns ( 49.55 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.888 ns" { scan_led:inst1|disp_dat[0] scan_led:inst1|Mux~261 scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.888 ns" { scan_led:inst1|disp_dat[0] scan_led:inst1|Mux~261 scan_led:inst1|count[2] } { 0.000ns 0.966ns 0.465ns } { 0.000ns 0.590ns 0.867ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.000ns 4.310ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|disp_dat[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|disp_dat[0] } { 0.000ns 4.310ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.888 ns" { scan_led:inst1|disp_dat[0] scan_led:inst1|Mux~261 scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.888 ns" { scan_led:inst1|disp_dat[0] scan_led:inst1|Mux~261 scan_led:inst1|count[2] } { 0.000ns 0.966ns 0.465ns } { 0.000ns 0.590ns 0.867ns } } }  } 0}