dled.tan.qmsg

来自「很多vhdl例程代码」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITDB_FULL_SLACK_RESULT" "clock_48M register int_div:inst\|Counter\[2\] register int_div:inst\|Counter\[7\] 14.715 ns " "Info: Slack time is 14.715 ns for clock \"clock_48M\" between source register \"int_div:inst\|Counter\[2\]\" and destination register \"int_div:inst\|Counter\[7\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "189.21 MHz 5.285 ns " "Info: Fmax is 189.21 MHz (period= 5.285 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock_48M 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock_48M\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock_48M 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock_48M\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M destination 2.925 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_48M\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 18; CLK Node = 'clock_48M'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { clock_48M } "NODE_NAME" } "" } } { "dled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/dled.bdf" { { 96 -64 104 112 "clock_48M" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns int_div:inst\|Counter\[7\] 2 REG LC_X11_Y11_N0 4 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X11_Y11_N0; Fanout = 4; REG Node = 'int_div:inst\|Counter\[7\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "1.456 ns" { clock_48M int_div:inst|Counter[7] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[7] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M source 2.925 ns - Longest register " "Info: - Longest clock path from clock \"clock_48M\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 18; CLK Node = 'clock_48M'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { clock_48M } "NODE_NAME" } "" } } { "dled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/dled.bdf" { { 96 -64 104 112 "clock_48M" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns int_div:inst\|Counter\[2\] 2 REG LC_X11_Y11_N3 4 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X11_Y11_N3; Fanout = 4; REG Node = 'int_div:inst\|Counter\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "1.456 ns" { clock_48M int_div:inst|Counter[2] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[2] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[7] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[2] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[7] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[2] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.024 ns - Longest register register " "Info: - Longest register to register delay is 5.024 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|Counter\[2\] 1 REG LC_X11_Y11_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y11_N3; Fanout = 4; REG Node = 'int_div:inst\|Counter\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { int_div:inst|Counter[2] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.547 ns) + CELL(0.583 ns) 2.130 ns int_div:inst\|add~283 2 COMB LC_X10_Y12_N4 6 " "Info: 2: + IC(1.547 ns) + CELL(0.583 ns) = 2.130 ns; Loc. = LC_X10_Y12_N4; Fanout = 6; COMB Node = 'int_div:inst\|add~283'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.130 ns" { int_div:inst|Counter[2] int_div:inst|add~283 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.751 ns int_div:inst\|add~261 3 COMB LC_X10_Y12_N9 1 " "Info: 3: + IC(0.000 ns) + CELL(0.621 ns) = 2.751 ns; Loc. = LC_X10_Y12_N9; Fanout = 1; COMB Node = 'int_div:inst\|add~261'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "0.621 ns" { int_div:inst|add~283 int_div:inst|add~261 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.535 ns) + CELL(0.738 ns) 5.024 ns int_div:inst\|Counter\[7\] 4 REG LC_X11_Y11_N0 4 " "Info: 4: + IC(1.535 ns) + CELL(0.738 ns) = 5.024 ns; Loc. = LC_X11_Y11_N0; Fanout = 4; REG Node = 'int_div:inst\|Counter\[7\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.273 ns" { int_div:inst|add~261 int_div:inst|Counter[7] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.942 ns 38.65 % " "Info: Total cell delay = 1.942 ns ( 38.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.082 ns 61.35 % " "Info: Total interconnect delay = 3.082 ns ( 61.35 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.024 ns" { int_div:inst|Counter[2] int_div:inst|add~283 int_div:inst|add~261 int_div:inst|Counter[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.024 ns" { int_div:inst|Counter[2] int_div:inst|add~283 int_div:inst|add~261 int_div:inst|Counter[7] } { 0.000ns 1.547ns 0.000ns 1.535ns } { 0.000ns 0.583ns 0.621ns 0.738ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[7] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[2] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.024 ns" { int_div:inst|Counter[2] int_div:inst|add~283 int_div:inst|add~261 int_div:inst|Counter[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.024 ns" { int_div:inst|Counter[2] int_div:inst|add~283 int_div:inst|add~261 int_div:inst|Counter[7] } { 0.000ns 1.547ns 0.000ns 1.535ns } { 0.000ns 0.583ns 0.621ns 0.738ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "int_div:inst\|ClockOut register scan_led:inst1\|count\[2\] register scan_led:inst1\|count\[2\] 1.032 ns " "Info: Minimum slack time is 1.032 ns for clock \"int_div:inst\|ClockOut\" between source register \"scan_led:inst1\|count\[2\]\" and destination register \"scan_led:inst1\|count\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.823 ns + Shortest register register " "Info: + Shortest register to register delay is 0.823 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan_led:inst1\|count\[2\] 1 REG LC_X27_Y12_N3 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y12_N3; Fanout = 10; REG Node = 'scan_led:inst1\|count\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(0.309 ns) 0.823 ns scan_led:inst1\|count\[2\] 2 REG LC_X27_Y12_N3 10 " "Info: 2: + IC(0.514 ns) + CELL(0.309 ns) = 0.823 ns; Loc. = LC_X27_Y12_N3; Fanout = 10; REG Node = 'scan_led:inst1\|count\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "0.823 ns" { scan_led:inst1|count[2] scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 37.55 % " "Info: Total cell delay = 0.309 ns ( 37.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.514 ns 62.45 % " "Info: Total interconnect delay = 0.514 ns ( 62.45 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "0.823 ns" { scan_led:inst1|count[2] scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.823 ns" { scan_led:inst1|count[2] scan_led:inst1|count[2] } { 0.0ns 0.514ns } { 0.0ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination int_div:inst\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"int_div:inst\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source int_div:inst\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"int_div:inst\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst\|ClockOut destination 5.021 ns + Longest register " "Info: + Longest clock path from clock \"int_div:inst\|ClockOut\" to destination register is 5.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|ClockOut 1 CLK LC_X11_Y12_N5 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y12_N5; Fanout = 13; CLK Node = 'int_div:inst\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { int_div:inst|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.310 ns) + CELL(0.711 ns) 5.021 ns scan_led:inst1\|count\[2\] 2 REG LC_X27_Y12_N3 10 " "Info: 2: + IC(4.310 ns) + CELL(0.711 ns) = 5.021 ns; Loc. = LC_X27_Y12_N3; Fanout = 10; REG Node = 'scan_led:inst1\|count\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.16 % " "Info: Total cell delay = 0.711 ns ( 14.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.310 ns 85.84 % " "Info: Total interconnect delay = 4.310 ns ( 85.84 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.0ns 4.31ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst\|ClockOut source 5.021 ns - Shortest register " "Info: - Shortest clock path from clock \"int_div:inst\|ClockOut\" to source register is 5.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|ClockOut 1 CLK LC_X11_Y12_N5 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y12_N5; Fanout = 13; CLK Node = 'int_div:inst\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { int_div:inst|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.310 ns) + CELL(0.711 ns) 5.021 ns scan_led:inst1\|count\[2\] 2 REG LC_X27_Y12_N3 10 " "Info: 2: + IC(4.310 ns) + CELL(0.711 ns) = 5.021 ns; Loc. = LC_X27_Y12_N3; Fanout = 10; REG Node = 'scan_led:inst1\|count\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.16 % " "Info: Total cell delay = 0.711 ns ( 14.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.310 ns 85.84 % " "Info: Total interconnect delay = 4.310 ns ( 85.84 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.0ns 4.31ns } { 0.0ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.0ns 4.31ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.0ns 4.31ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 40 -1 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.0ns 4.31ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.0ns 4.31ns } { 0.0ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "0.823 ns" { scan_led:inst1|count[2] scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.823 ns" { scan_led:inst1|count[2] scan_led:inst1|count[2] } { 0.0ns 0.514ns } { 0.0ns 0.309ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.0ns 4.31ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.021 ns" { int_div:inst|ClockOut scan_led:inst1|count[2] } { 0.0ns 4.31ns } { 0.0ns 0.711ns } } }  } 0}