dled.tan.qmsg

来自「很多vhdl例程代码」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock_48M register int_div:inst\|Counter\[0\] register int_div:inst\|Counter\[0\] 1.874 ns " "Info: Minimum slack time is 1.874 ns for clock \"clock_48M\" between source register \"int_div:inst\|Counter\[0\]\" and destination register \"int_div:inst\|Counter\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.665 ns + Shortest register register " "Info: + Shortest register to register delay is 1.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|Counter\[0\] 1 REG LC_X10_Y12_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y12_N1; Fanout = 5; REG Node = 'int_div:inst\|Counter\[0\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(0.590 ns) 1.114 ns int_div:inst\|add~291 2 COMB LC_X10_Y12_N2 1 " "Info: 2: + IC(0.524 ns) + CELL(0.590 ns) = 1.114 ns; Loc. = LC_X10_Y12_N2; Fanout = 1; COMB Node = 'int_div:inst\|add~291'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "1.114 ns" { int_div:inst|Counter[0] int_div:inst|add~291 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.115 ns) 1.665 ns int_div:inst\|Counter\[0\] 3 REG LC_X10_Y12_N1 5 " "Info: 3: + IC(0.436 ns) + CELL(0.115 ns) = 1.665 ns; Loc. = LC_X10_Y12_N1; Fanout = 5; REG Node = 'int_div:inst\|Counter\[0\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "0.551 ns" { int_div:inst|add~291 int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.705 ns 42.34 % " "Info: Total cell delay = 0.705 ns ( 42.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.960 ns 57.66 % " "Info: Total interconnect delay = 0.960 ns ( 57.66 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "1.665 ns" { int_div:inst|Counter[0] int_div:inst|add~291 int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.665 ns" { int_div:inst|Counter[0] int_div:inst|add~291 int_div:inst|Counter[0] } { 0.0ns 0.524ns 0.436ns } { 0.0ns 0.59ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock_48M 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock_48M\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock_48M 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock_48M\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M destination 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clock_48M\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 18; CLK Node = 'clock_48M'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { clock_48M } "NODE_NAME" } "" } } { "dled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/dled.bdf" { { 96 -64 104 112 "clock_48M" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns int_div:inst\|Counter\[0\] 2 REG LC_X10_Y12_N1 5 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X10_Y12_N1; Fanout = 5; REG Node = 'int_div:inst\|Counter\[0\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "1.456 ns" { clock_48M int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[0] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M source 2.925 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_48M\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 18; CLK Node = 'clock_48M'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { clock_48M } "NODE_NAME" } "" } } { "dled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/dled.bdf" { { 96 -64 104 112 "clock_48M" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns int_div:inst\|Counter\[0\] 2 REG LC_X10_Y12_N1 5 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X10_Y12_N1; Fanout = 5; REG Node = 'int_div:inst\|Counter\[0\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "1.456 ns" { clock_48M int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[0] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[0] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[0] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 37 -1 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[0] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[0] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "1.665 ns" { int_div:inst|Counter[0] int_div:inst|add~291 int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.665 ns" { int_div:inst|Counter[0] int_div:inst|add~291 int_div:inst|Counter[0] } { 0.0ns 0.524ns 0.436ns } { 0.0ns 0.59ns 0.115ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[0] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "2.925 ns" { clock_48M int_div:inst|Counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock_48M clock_48M~out0 int_div:inst|Counter[0] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock_48M seg\[3\] scan_led:inst1\|disp_dat\[3\] 15.543 ns register " "Info: tco from clock \"clock_48M\" to destination pin \"seg\[3\]\" through register \"scan_led:inst1\|disp_dat\[3\]\" is 15.543 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M source 9.044 ns + Longest register " "Info: + Longest clock path from clock \"clock_48M\" to source register is 9.044 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 18; CLK Node = 'clock_48M'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/" "" "" { clock_48M } "NODE_NAME" } "" } } { "dled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/dled.bdf" { { 96 -64 104 112 "clock_48M" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns int_div:inst\|Temp1 2 CLK LC_X12_Y12_N9 2 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X12_Y12_N9; Fanout = 2; CLK Node = 'int_div:inst\|Temp1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/db/dled_cmp.qrpt" Compiler "dled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/