hdb3system.vhd

来自「hDB3的编解码模块 是在maxplusII 下验证过的 并且下到片子中都正」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity hdb3system is
port(reset,clk:in std_logic;
     dout,my: out std_logic;
     doutb: out std_logic_vector(1 downto 0));
end;

architecture rtl of hdb3system is
signal d:std_logic;
signal d5:std_logic_vector(1 downto 0);
component hdb3 is
port(reset,clk,datain:in std_logic;
     dout: out std_logic_vector(1 downto 0));
end component;

component M1 IS
 PORT(reset,CLK: IN STD_LOGIC;
            Y: OUT STD_LOGIC);
END component;

component hdb3decoder is
port(clk:in std_logic;
     datain:in std_logic_vector(1 downto 0);
     dout:out std_logic);
end component;
begin

d1:hdb3 port map(reset,clk,d,d5);
  doutb<=d5;
d2:M1   port map(reset,clk,d);
  my<=d;
d3:hdb3decoder port map(clk,d5,dout);
end;