hdb3a.vhd

来自「hDB3的编解码模块 是在maxplusII 下验证过的 并且下到片子中都正」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity hdb3a is
port(reset,clk,datain: in std_logic;
     dout: out std_logic_vector(1 downto 0));
end entity;

architecture rtl of hdb3a is
signal counter:integer range 0 to 3;
begin
process(reset,clk,datain) is 
begin
if reset='0' then counter<=0;dout<="00";
elsif(clk='1' and clk'event) then
  if datain='0' then
    counter<=counter+1;
    if counter=3 then     --连4个0了
       dout<="11"; counter<=0;
    else
       dout<="00";        --没连4个0
    end if;
  else
    dout<="01";   --1 码
    counter<=0;
  end if;
end if;
end process;
end;