mux.vhd

来自「hDB3的编解码模块 是在maxplusII 下验证过的 并且下到片子中都正」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mux is
port(a:in std_logic_vector(11 downto 0);
     sel:in std_logic;
     c:out std_logic_vector(11 downto 0));
end mux;

architecture bhv of mux is
begin
  process(a,sel) is
  begin
  if(sel='1') then
     c<=a;
  elsif(sel='0') then
     c<="000000000000";
  end if;
  end process;

  end bhv;