hdb3decoder.vhd

hDB3的编解码模块 是在maxplusII 下验证过的 并且下到片子中都正确

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity hdb3decoder is
port(clk:in std_logic;
     datain:in std_logic_vector(1 downto 0);
     dout:out std_logic);
end hdb3decoder;

architecture rtl of hdb3decoder is
signal D1,D0:std_logic_vector(3 downto 0);
signal t:std_logic_vector(1 downto 0);
begin
 t<=datain;
process(clk,datain)is
begin
if(clk='1' and clk'event)then
  D1(2 downto 1)<=D1(3 downto 2);
  D0(2 downto 1)<=D0(3 downto 2);
end if;
end process;

process(clk,datain) is
begin
if(clk='1' and clk'event)then 
if ((t="11" and D1(3 downto 0)="0001" and D0(3 downto 0)="0001")or(t="01" and D1(3 downto 0)="0000" and D0(3 downto 0)="0001"))then
      D1(3)<='0';D0(3)<='0';D1(0)<=D1(1);D0(0)<=D0(1);
elsif((t="11" and D1(3 downto 1)="001" and D0(3 downto 1)="001")or(t="01" and D1(3 downto 1)="000" and D0(3 downto 1)="001"))then
      D1(3)<='0';D0(3)<='0';D1(0)<='0';D0(0)<='0';
else
      D1(3)<=t(1);D0(3)<=t(0);D1(0)<=D1(1);D0(0)<=D0(1);
end if;
end if;
end process;

process(clk)is
begin
if(clk='1' and clk'event) then
 if((D1(0)='1' and D0(0)='1')or(D1(0)='0' and D0(0)='1'))  then
   dout<='1';
 else dout<='0';
 end if;
end if;
end process;

end;