add_fix.v

来自「IEEE754 floating point adder」· Verilog 代码 · 共 45 行

/* ------------------------------------------------------------
// Module: ADD_Fix (Form: fix-point)
// Edition: one
// Matlab code: None
// C code: None
// Architecture diagram: None 
// Date: 2007/12/12
// Update: 2007/12/12
// ------------------------------------------------------------ */



module ADD_Fix (In_x,In_y,Out);



/* ------------------------------------------------------------
// Parameters definition
// ------------------------------------------------------------ */

parameter DATA_WIDTH=50;	// bus width for data
	  	  
/* ------------------------------------------------------------
// I/O pin declaration
// ------------------------------------------------------------ */

input [DATA_WIDTH-1:0] In_x,In_y;			

output [DATA_WIDTH-1:0] Out;		   

/* ------------------------------------------------------------
// Connection wire declaration
// ------------------------------------------------------------ */

wire [DATA_WIDTH-1:0] Out;		

/* ------------------------------------------------------------
// Combinational logic
// ------------------------------------------------------------ */

assign Out = In_x+In_y;



endmodule