ieee_to_twos_compl.v

来自「IEEE754 floating point adder」· Verilog 代码 · 共 48 行

/* ------------------------------------------------------------
// MODULE: IEEE_to_Twos_compl (no clock )
// Edition: one
// Matlab Code:  None
// C Code: None
// Architecture Diagram: None
// Date: 2008/01/30
// Update: 2008/01/30	   
// ------------------------------------------------------------ */
module IEEE_to_Twos_compl(data_in,data_out);
/* ------------------------------------------------------------
// Parameters definition
// ------------------------------------------------------------ */

parameter data_lng=32,//data_in length
	  exp_lng=7,//data_in exponent part length
	  sgnfc_lng=25;//data_in significant part length
 
/* ------------------------------------------------------------
// I/O declaration
// ------------------------------------------------------------ */
input [data_lng-1:0]data_in; //include sgnfc and exp part

output [data_lng-1:0]data_out; // data_out
/* ------------------------------------------------------------
// Connection wire declaration
// ------------------------------------------------------------ */
wire sign;
wire [sgnfc_lng-1:0]compl_data_sgnfc,data_sgnfc;

wire [sgnfc_lng-1:0]real_data_sgnfc;
wire [data_lng-1:0]data_out;
/* ------------------------------------------------------------
// Module instance
// ------------------------------------------------------------ */


assign sign=data_in[data_lng-1];

assign data_sgnfc=data_in[data_lng-1:exp_lng];

assign compl_data_sgnfc={sign,(~data_sgnfc[sgnfc_lng-2:0]+1'b1)};

assign real_data_sgnfc=(sign)?compl_data_sgnfc:data_sgnfc;

assign data_out={real_data_sgnfc,data_in[exp_lng-1:0]};

endmodule