2倍分频的verilog.txt

来自「这是关于2分频的vhdl实现和verilog hdl实现」· 文本 代码 · 共 17 行

module divide2( clk , clk_o, reset);
   input     clk , reset;
   output   clk_o;
   wire in;  
reg out ;
   always @ ( posedge clk or posedge reset)
     if ( reset)
       out <= 0;
         else
           out <= in;
       assign in = ~out;
       assign clk_o = out;
     endmodule