division_2.txt

来自「这是关于2分频的vhdl实现和verilog hdl实现」· 文本 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity division_2 is
PORT (CLK:IN STD_LOGIC;
clk2 :OUT STD_LOGIC);
end division_2;

architecture Behavioral of division_2 is
signal temp:std_logic;

begin
p:process(clk)
begin
if clk' event and clk='0' then
temp<=not temp;
end if;
end process;


clk2<=temp;

end Behavioral;