division5.txt

5倍分频的vhdl代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity division5 is
port (clk: in std_logic;
      out1: out std_logic);
end division5;


architecture Behavioral of division5 is

signal division2,division4 :std_logic:='0';
signal temp1,temp2:integer range 0 to 10;

begin
p1:process(clk)
begin
if rising_edge(clk) then
temp1<=temp1+1;
if temp1=2 then
division2<='1';
elsif temp1=4 then
division2<='0';
temp1<=0;
end if;
end if;
end process p1;

p2:process(clk)
begin
if clk'event and clk='0' then
temp2<=temp2+1;
if temp2=2 then
division4<='1';
elsif temp2=4 then
division4<='0';
temp2<=0;
end if;
end if;
end process p2;

p3:process(division2,division4)
begin
out1<=division2 or division4;
end process p3;

end Behavioral; 

把上面的部分截取就可以得到异步的.




verilog 调用VHDL例子
`timescale 1ns/100ps 


module testbench(); 
reg clk;
wire clk5;

always 
begin
#1 clk <= ~clk ;
end


initial 
begin
clk <= 1'b0;
end

initial 
begin
#10000000; //10ms
$display("over");
$finish();
end


division5 division5_inst(clk,clk5);


endmodule