mac_tx_ctrl.v

verilog实现的异步UART代码

                    Next_state=StateData;       
            StatePAD:
                if (!FullDuplex&&Collision)
                    Next_state=StateJam; 
                else if (IPLengthCounter>=59)
                    Next_state=StateFCS;        
                else 
                    Next_state=Current_state;
            StateJam:
                if (RetryCnt<=MaxRetry&&JamCounter==16) 
                    Next_state=StateBackOff;
                else if (RetryCnt>MaxRetry)
                    Next_state=StateJamDrop;
                else
                    Next_state=Current_state;
            StateBackOff:
                if (Random_time_meet)
                    Next_state  =StateDefer;
                else 
                    Next_state  =Current_state;
            StateFCS:
                if (!FullDuplex&&Collision)
                    Next_state  =StateJam;
                else if (CRC_end)
                    Next_state  =StateSwitchNext;
                else
                    Next_state  =Current_state;
            StateFFEmptyDrop:
                if (Fifo_eop)
                    Next_state  =StateSwitchNext;
                else
                    Next_state  =Current_state;             
            StateJamDrop:
                if (Fifo_eop)
                    Next_state  =StateSwitchNext;
                else
                    Next_state  =Current_state;
            StateSwitchNext:
                    Next_state  =StateDefer;            
            default:
                Next_state  =StateDefer;
        endcase

 
        
always @ (posedge Clk or posedge Reset)
    if (Reset)
        JamCounter      <=0;
    else if (Current_state!=StateJam)
        JamCounter      <=0;
    else if (Current_state==StateJam)
        JamCounter      <=JamCounter+1;
        
             
always @ (posedge Clk or posedge Reset)
    if (Reset)
        RetryCnt        <=0;
    else if (Current_state==StateSwitchNext)
        RetryCnt        <=0;
    else if (Current_state==StateJam&&Next_state==StateBackOff)
        RetryCnt        <=RetryCnt + 1;
            
always @ (posedge Clk or posedge Reset)
    if (Reset)
        IFG_counter     <=0;
    else if (Current_state!=StateIFG)
        IFG_counter     <=0;
    else 
        IFG_counter     <=IFG_counter + 1;

always @ (posedge Clk or posedge Reset)
    if (Reset)
        Preamble_counter    <=0;
    else if (Current_state!=StatePreamble)
        Preamble_counter    <=0;
    else
        Preamble_counter    <=Preamble_counter+ 1;
        
always @ (posedge Clk or posedge Reset)
    if (Reset)      
        PktDrpEvenPtr       <=0;
    else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop)
        PktDrpEvenPtr       <=~PktDrpEvenPtr;
//******************************************************************************    
//generate output signals                                                           
//****************************************************************************** 
//CRC related
always @(Current_state)
    if (Current_state==StateSFD)
        CRC_init    =1;
    else
        CRC_init    =0;
        
assign Frame_data=TxD_tmp;

always @(Current_state)
    if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD)
        Data_en     =1;
    else
        Data_en     =0;
        
always @(Current_state)
    if (Current_state==StateFCS)
        CRC_rd      =1;
    else
        CRC_rd      =0;     
    
//Ramdon_gen interface
always @(Current_state or Next_state)
    if (Current_state==StateJam&&Next_state==StateBackOff)
        Random_init =1;
    else
        Random_init =0; 

//MAC_rx_FF
//data have one cycle delay after fifo read signals  
always @ (*)
    if (Current_state==StateData ||
        Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen||xon_gen))  ||
        Current_state==StateJamDrop&&PktDrpEvenPtr||
        Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )
        Fifo_rd     =1;
    else
        Fifo_rd     =0; 
        
always @ (Current_state)
    if (Current_state==StateSwitchNext)     
        Fifo_rd_finish  =1;
    else
        Fifo_rd_finish  =0;
        
always @ (Current_state)
    if (Current_state==StateJam)        
        Fifo_rd_retry   =1;
    else
        Fifo_rd_retry   =0;     
//RMII
always @(Current_state)
    if (Current_state==StatePreamble||Current_state==StateSFD||
        Current_state==StateData||Current_state==StateSendPauseFrame||
        Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)
        TxEn_tmp    =1;
    else
        TxEn_tmp    =0;

//gen txd data      
always @(*)
    case (Current_state)
        StatePreamble:
            TxD_tmp =8'h55;
        StateSFD:
            TxD_tmp =8'hd5;
        StateData:
            if (Src_MAC_ptr&&MAC_tx_add_en)       
                TxD_tmp =MAC_tx_addr_data;
            else
                TxD_tmp =Fifo_data;
        StateSendPauseFrame:
            if (Src_MAC_ptr&&MAC_tx_add_en)       
                TxD_tmp =MAC_tx_addr_data;
            else 
                case (IPLengthCounter)
                    7'd0:   TxD_tmp =8'h01;
                    7'd1:   TxD_tmp =8'h80;
                    7'd2:   TxD_tmp =8'hc2;
                    7'd3:   TxD_tmp =8'h00;
                    7'd4:   TxD_tmp =8'h00;
                    7'd5:   TxD_tmp =8'h01;
                    7'd12:  TxD_tmp =8'h88;//type
                    7'd13:  TxD_tmp =8'h08;//
                    7'd14:  TxD_tmp =8'h00;//opcode
                    7'd15:  TxD_tmp =8'h01;
                    7'd16:  TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8];
                    7'd17:  TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0];
//                    7'd60:  TxD_tmp =8'h26;
//                    7'd61:  TxD_tmp =8'h6b;
//                    7'd62:  TxD_tmp =8'hae;
//                    7'd63:  TxD_tmp =8'h0a;
                    default:TxD_tmp =0;
                endcase
        
        StatePAD:
                TxD_tmp =8'h00; 
        StateJam:
                TxD_tmp =8'h01; //jam sequence
        StateFCS:
            TxD_tmp =CRC_out;
        default:
            TxD_tmp =2'b0;
    endcase
always @ (posedge Clk or posedge Reset)
    if (Reset)
        begin
        TxD     <=0;
        TxEn    <=0;
        end
    else
        begin
        TxD     <=TxD_tmp;
        TxEn    <=TxEn_tmp;
        end     
//RMON


always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_pkt_length_rmon      <=0;
    else if (Current_state==StateSFD)
        Tx_pkt_length_rmon      <=0;
    else if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD||Current_state==StateFCS)
        Tx_pkt_length_rmon      <=Tx_pkt_length_rmon+1;
        
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_apply_rmon_tmp       <=0;
    else if ((Fifo_eop&&Current_state==StateJamDrop)||
             (Fifo_eop&&Current_state==StateFFEmptyDrop)||
             CRC_end)
        Tx_apply_rmon_tmp       <=1;
    else
        Tx_apply_rmon_tmp       <=0; 

always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_apply_rmon_tmp_pl1   <=0;
    else
        Tx_apply_rmon_tmp_pl1   <=Tx_apply_rmon_tmp;
        
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_apply_rmon       <=0;
    else if ((Fifo_eop&&Current_state==StateJamDrop)||
             (Fifo_eop&&Current_state==StateFFEmptyDrop)||
             CRC_end)
        Tx_apply_rmon       <=1;
    else if (Tx_apply_rmon_tmp_pl1)
        Tx_apply_rmon       <=0;
        
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_pkt_err_type_rmon    <=0;    
    else if(Fifo_eop&&Current_state==StateJamDrop)
        Tx_pkt_err_type_rmon    <=3'b001;//
    else if(Fifo_eop&&Current_state==StateFFEmptyDrop)
        Tx_pkt_err_type_rmon    <=3'b010;//underflow
    else if(Fifo_eop&&Fifo_data_err_full)
        Tx_pkt_err_type_rmon    <=3'b011;//overflow
    else if(CRC_end)
        Tx_pkt_err_type_rmon    <=3'b100;//normal
        
always @ (posedge Clk or posedge Reset)
    if (Reset)
        MAC_header_slot_tmp <=0;
    else if(Current_state==StateSFD&&Next_state==StateData)
        MAC_header_slot_tmp <=1;    
    else
        MAC_header_slot_tmp <=0;
        
always @ (posedge Clk or posedge Reset)
    if (Reset)
        MAC_header_slot     <=0;
    else 
        MAC_header_slot     <=MAC_header_slot_tmp;

always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_pkt_type_rmon    <=0;
    else if (Current_state==StateSendPauseFrame)
        Tx_pkt_type_rmon    <=3'b100;
    else if(MAC_header_slot)
        Tx_pkt_type_rmon    <={1'b0,TxD[7:6]};

       
always @(Tx_pkt_length_rmon)
    if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)
        Src_MAC_ptr         =1;
    else
        Src_MAC_ptr         =0;        

//MAC_tx_addr_add  
always @ (posedge Clk or posedge Reset)
    if (Reset)
        MAC_tx_addr_rd  <=0;
    else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))
        MAC_tx_addr_rd  <=1;
    else
        MAC_tx_addr_rd  <=0;

always @ (Tx_pkt_length_rmon or Fifo_rd)
    if ((Tx_pkt_length_rmon==3)&&Fifo_rd)
        MAC_tx_addr_init=1;
    else
        MAC_tx_addr_init=0;

//flow control
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta_sub    <=0;
    else if(pause_counter==512/8)
        pause_quanta_sub    <=1;
    else
        pause_quanta_sub    <=0;

 
always @ (posedge Clk or posedge Reset)
    if (Reset) 
        xoff_gen_complete   <=0;
    else if(Current_state==StateDefer&&xoff_gen)
        xoff_gen_complete   <=1;
    else
        xoff_gen_complete   <=0;
    
    
always @ (posedge Clk or posedge Reset)
    if (Reset) 
        xon_gen_complete    <=0;
    else if(Current_state==StateDefer&&xon_gen)
        xon_gen_complete    <=1;
    else
        xon_gen_complete    <=0;

endmodule