mac_rx_ff.v

verilog实现的异步UART代码

    if (Reset)
        Fifo_data_dl1   <=0;
    else 
        Fifo_data_dl1   <=Fifo_data;
        
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte3     <=0;
    else if (Current_state==State_byte3&&Fifo_data_en_dl1)
        Fifo_data_byte3     <=Fifo_data_dl1;

always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte2     <=0;
    else if (Current_state==State_byte2&&Fifo_data_en_dl1)
        Fifo_data_byte2     <=Fifo_data_dl1;
        
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte1     <=0;
    else if (Current_state==State_byte1&&Fifo_data_en_dl1)
        Fifo_data_byte1     <=Fifo_data_dl1;

always @ (* )
    case (Current_state)
        State_be0:
            Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};       
        State_be1:
            Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
        State_be2:
            Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
        State_be3:
            Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
        default:
            Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
    endcase
    
always @ (*)
    if (Current_state==State_be0||Current_state==State_be1||
       Current_state==State_be2||Current_state==State_be3||
      (Current_state==State_byte0&&Fifo_data_en))
        Wr_en_tmp   =1;
    else 
        Wr_en_tmp   =0; 

always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Din_tmp_reg <=0;
    else if(Wr_en_tmp)
        Din_tmp_reg <=Din_tmp;  
        
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Wr_en_ptr   <=0;
    else if(Current_state==State_idle)
        Wr_en_ptr   <=0;    
    else if(Wr_en_tmp)
        Wr_en_ptr   <=1;

//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        begin
        Wr_en           <=0;
        Din             <=0;
        end
    else if(RX_APPEND_CRC)
        begin
        Wr_en           <=Wr_en_tmp;
        Din             <=Din_tmp;
        end         
    else
        begin
        Wr_en           <=Wr_en_tmp&&Wr_en_ptr;
        Din             <={Din_tmp[35:32],Din_tmp_reg[31:0]};
        end                                 
        
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Packet_number_add_tmp   <=0;
    else if (Current_state==State_be0||Current_state==State_be1||
             Current_state==State_be2||Current_state==State_be3)
        Packet_number_add_tmp   <=1;
    else 
        Packet_number_add_tmp   <=0;
        
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        begin
        Packet_number_add_tmp_dl1   <=0;
        Packet_number_add_tmp_dl2   <=0;
        end
    else
        begin
        Packet_number_add_tmp_dl1   <=Packet_number_add_tmp;
        Packet_number_add_tmp_dl2   <=Packet_number_add_tmp_dl1;
        end     
        
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.       
//expand to two cycles long almost=16 ns
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles       
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Packet_number_add   <=0;
    else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
        Packet_number_add   <=1;
    else 
        Packet_number_add   <=0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//******************************************************************************
//domain Clk_SYS,read data from dprom.b-port for read
//******************************************************************************


always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Current_state_SYS   <=SYS_idle;
    else 
        Current_state_SYS   <=Next_state_SYS;
        
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
    case (Current_state_SYS)
        SYS_idle:
			if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
                Next_state_SYS  =SYS_read;
		    else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
		        Next_state_SYS	=FF_emtpy_err;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_read:
            if (!Rx_mac_rd)
                Next_state_SYS  =SYS_pause;
            else if (Dout[35])                
                Next_state_SYS  =SYS_wait_end;
            else if (Empty)
                Next_state_SYS  =FF_emtpy_err;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_pause:
            if (Rx_mac_rd)                            
                Next_state_SYS  =SYS_read;         
            else                                   
                Next_state_SYS  =Current_state_SYS;
        FF_emtpy_err:
            if (!Empty)
                Next_state_SYS  =SYS_read;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_wait_end:
            if (!Rx_mac_rd)
                Next_state_SYS  =SYS_idle;
            else
                Next_state_SYS  =Current_state_SYS;
        default:
                Next_state_SYS  =SYS_idle;
    endcase
    
        
//gen Rx_mac_ra 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Packet_number_add_dl1   <=0;
        Packet_number_add_dl2   <=0;
        end
    else 
        begin
        Packet_number_add_dl1   <=Packet_number_add;
        Packet_number_add_dl2   <=Packet_number_add_dl1;
        end
assign  Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;

always @ (Current_state_SYS or Next_state_SYS)
    if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
        Packet_number_sub       =1;
    else
        Packet_number_sub       =0;
        
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Packet_number_inFF      <=0;
    else if (Packet_number_add_edge&&!Packet_number_sub)
        Packet_number_inFF      <=Packet_number_inFF + 1;
	else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
        Packet_number_inFF      <=Packet_number_inFF - 1;

always @ (posedge Clk_SYS or posedge Reset)                                                         
    if (Reset)                                                                                      
        Fifo_data_count     <=0;                                                                    
    else                                                                                            
        Fifo_data_count     <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]; 

always @ (posedge Clk_SYS or posedge Reset)                                                         
    if (Reset) 
        begin
        Rx_Hwmark_pl        <=0;
        Rx_Lwmark_pl        <=0;
        end
    else
        begin
        Rx_Hwmark_pl        <=Rx_Hwmark;
        Rx_Lwmark_pl        <=Rx_Lwmark;
        end   
        
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)  
        Rx_mac_ra   <=0;
    else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
        Rx_mac_ra   <=0;
    else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
        Rx_mac_ra   <=1;

        
//control Add_rd signal;
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_rd      <=0;
    else if (Current_state_SYS==SYS_read&&!Dout[35])  
        Add_rd      <=Add_rd + 1;

//
always @ (posedge Reset or posedge Clk_SYS)
    if (Reset)
        Add_rd_gray         <=0;
    else 
		begin
		Add_rd_gray[`MAC_RX_FF_DEPTH-1]	<=Add_rd[`MAC_RX_FF_DEPTH-1];
		for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
		Add_rd_gray[i]			<=Add_rd[i+1]^Add_rd[i];
		end
//

always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_gray_dl1     <=0;
    else
        Add_wr_gray_dl1     <=Add_wr_gray;
            
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_jump_rd_pl1  <=0;
    else        
        Add_wr_jump_rd_pl1  <=Add_wr_jump;	
            
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_ungray       =0;
    else if (!Add_wr_jump_rd_pl1)       
		begin
		Add_wr_ungray[`MAC_RX_FF_DEPTH-1]	=Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];	
		for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
			Add_wr_ungray[i]	=Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];	
		end                    
//empty signal gen  
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)      
        Empty   <=1;
    else if (Add_rd==Add_wr_ungray)
        Empty   <=1;
    else
        Empty   <=0;



always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Dout_dl1    <=0;
    else
        Dout_dl1    <=Dout; 

assign  Rx_mac_data     =Dout_dl1[31:0];
assign  Rx_mac_BE       =Dout_dl1[33:32];
assign  Rx_mac_eop      =Dout_dl1[35];

//aligned to Addr_rd 
always @ (posedge Clk_SYS or posedge Reset) 
    if (Reset)
        Rx_mac_pa_tmp   <=0;    
    else if (Current_state_SYS==SYS_read&&!Dout[35])         
        Rx_mac_pa_tmp   <=1;
    else
        Rx_mac_pa_tmp   <=0;



always @ (posedge Clk_SYS or posedge Reset) 
    if (Reset)
        Rx_mac_pa   <=0;
    else 
        Rx_mac_pa   <=Rx_mac_pa_tmp;
    

    
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_sop_tmp      <=0;
    else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
        Rx_mac_sop_tmp      <=1;
    else
        Rx_mac_sop_tmp      <=0;
        

        
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Rx_mac_sop_tmp_dl1  <=0;
        Rx_mac_sop          <=0;
        end
    else 
        begin
        Rx_mac_sop_tmp_dl1  <=Rx_mac_sop_tmp;
        Rx_mac_sop          <=Rx_mac_sop_tmp_dl1;
        end



//******************************************************************************

duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(          
.data_a         (Din        ), 
.wren_a         (Wr_en      ), 
.address_a      (Add_wr     ), 
.address_b      (Add_rd     ), 
.clock_a        (Clk_MAC    ), 
.clock_b        (Clk_SYS    ), 
.q_b            (Dout       ));

endmodule